71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
DIO_DIR1[7:6]
DIO_DIR1[3:0]
SFR91
R/W Programs the direction of DIO pins 15, 14 and 11 through 8. 1
indicates output. Ignored if the pin is not configured as I/O.
Note: Bit 4 and Bit 5 must be set to 1.
DIO_DIR2[1:0]
DIO_0[7:4]
SFRA1[5:0]
SFR80
R/W Programs the direction of DIO pins 17 and 16. 1 indicates output.
Ignored if the pin is not configured as I/O.
Note: Bit 2, Bit 3, Bit 4 and Bit 5 must be set to 1.
R/W Port 0
The value on the DIO pins. Pins configured as LCD will read
zero. When written, changes data on pins configured as
outputs. Pins configured as LCD or input will ignore writes.
DIO_1[7:6],
DIO_1[3:0]
SFR90
SFR90
R/W Port 1
R/W Port 1
DIO_2[1:0]
DIO_EEX
SFRA0[1:0]
2008[4]
R/W Port 2
R/W When set, converts DIO4 and DIO5 to interface with external
EEPROM. DIO4 becomes SCK and DIO5 becomes bi-directional SDA.
LCD_NUM must be less than 18.
DIO_PV
DIO_PW
2008[2]
2008[3]
R/W Causes VARPULSE to be output on DIO7, if DIO7 is configured as
output. LCD_NUM must be less than 15.
R/W Causes WPULSE to be output on DIO6, if DIO6 is configured as
output. LCD_NUM must be less than 17.
EEDATA[7:0]
EECTRL[7:0]
ECK_DIS
SFR 9E
SFR 9F
2005[5]
R/W Serial EEPROM interface data
R/W Serial EEPROM interface control
R/W Emulator clock disable. When one, the emulator clock is disabled.
This bit is to be used with caution! Inadvertently setting
this bit will inhibit access to the part with the ICE
interface and thus preclude flash erase and programming
operations. If ECK_DIS is set, it should be done at least 1000ms after
power-up to give emulators and programming devices enough time to
complete an erase operation.
EQU[2:0]
EX_XFR
EX_RTC
2000[7:5]
2002[0]
2002[1]
R/W Specifies the power equation to the CE.
R/W Interrupt enable bits. These bits enable the XFER_BUSY and the
RTC_1SEC interrupts to the MPU. Note that if either interrupt is to be
enabled, EX6 in the 80515 must also be set.
FIR_LEN
2005[4]
R/W The length of the ADC decimation FIR filter.
1: 22 ADC bits/3 CK32 cycles (384 CKFIR cycles),
0: 21 ADC bits/2 CK32 cycles (288 CKFIR cycles)
FLASH66Z
2005[1]
R/W Should be set to 1 to minimize supply current.
Page: 59 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
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