71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
PREBOOT
PRE_SAMPS[1:0]
SFR B2[7]
2001[7:6]
R
Indicates that the preboot sequence is active.
R/W Together w/ SUM_CYCLES, this value determines the number of
samples in one sum cycle between XFER interrupts for the CE.
Number of samples = PRE_SAMPS*SUM_CYCLES.
00-42, 01-50, 10-84, 11-100
RTC_SEC[5:0]
RTC_MINI[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2015
2016
2017
2018
2019
201A
201B
R/W The RTC interface. These are the ‘year’, ‘month’, ‘day’, ‘hour’, ‘minute’
and ‘second’ parameters for the RTC. The RTC is set by writing to
these registers. Year 00 is defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR
00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO 01 to 12
YR
00 to 256
RTC_DEC_SEC
RTC_INC_SEC
201C[1]
201C[0]
W
RTC time correction bits. Only one bit may be pulsed at a time. When
pulsed, causes the RTC time value to be incremented (or
decremented) by an additional second the next time the RTC_SEC
register is clocked. The pulse width may be any value. If an additional
correction is desired, the MPU must wait 2 seconds before pulsing one
of the bits again.
RTM_EN
2002[3]
R/W Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2060
2061
2062
2063
R/W Four RTM probes. Before each CE code pass, the values of these
R/W registers are serially output on the RTM pin. The RTM registers are
R/W ignored when RTM_EN=0.
R/W
SECURE
SFR B2[6]
R/W Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
SSI_EN
2070[7]
R/W Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and
SEG5 pins. If SSI_RDYEN is set, SEG6 is enabled also. The pins take
on the new functions SCLK, SSDATA, SFR, and SRDY, respectively.
When SSI_EN is high and LCD_EN is low, these pins are converted to
the SSI function, regardless of LCDEN and LCD_NUM. For proper
LCD operation, SSI_EN must not be high when LCD_EN is high.
SSI_10M
SSI_CKGATE
2070[6]
2070[5]
R/W SSI clock speed: 0: 5MHz, 1: 10MHz
R/W SSI gated clock enable. When low, the SCLK is continuous. When
high, the clock is held low when data is not being transferred.
SSI_FSIZE[1:0]
2070[4:3]
R/W SSI frame pulse format:
0: once at beginning of SSI sequence (whole block of data),
1: every 8 bits, 2: every 16 bits, 3: every 32 bits.
SSI_FPOL
SSI_RDYEN
2070[2]
2070[1]
R/W SFR pulse polarity: 0: positive, 1: negative
R/W SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is
configured as SRDY. Otherwise, it is an LCD driver.
SSI_RDYPOL
2070[0]
R/W SRDY polarity: 0: positive, 1: negative
Page: 62 of 95
© 2005-2007 TERIDIAN Semiconductor Corporation
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