TSC87251G1A
11.4. AC Characteristics – SSLC: SPI Interface
Definition of symbols
Table 48. SPI Interface Timing Symbol Definitions
Signals
Conditions
C
I
Clock
H
L
High
Data In
Data Out
Low
O
V
X
Valid
No Longer Valid
Timings
Table 49. SPI Interface AC Timing; V = 4.5 to 5.5 V, T = –40 to 85°C
DD
A
Symbol
Parameter
Min
Max
Unit
Master mode(1)
T
T
T
T
T
T
T
T
T
T
T
Clock Period
4
T
T
T
CHCH
CHCX
CLCX
OSC
Clock High Time
Clock Low Time
1.6
1.6
50
50
OSC
OSC
, T
IVCL IVCH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
ns
, T
CLIX CHIX
ns
ns
ns
µs
µs
ns
ns
CLOV, T
65
CHOV
, T
0
CLOX CHOX
ILIH
2
2
Input Data Fall Time
IHIL
Output Data Rise time
50
50
OLOH
Output Data Fall Time
OHOL
Notes:
1. Capacitive load on all pins= 100 pF in master mode.
43
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
