TSC87251G1A
Timings
Table 53. External Clock AC Timings; V = 4.5 to 5.5 V, T = –40 to +85°C
DD
A
Symbol
Parameter
Min
Max
Unit
F
Oscillator Frequency
High Time
24
MHz
ns
OSC
T
CHCX
10
10
3
T
CLCX
T
CLCH
T
CHCL
Low Time
ns
Rise Time
ns
Fall Time
3
ns
Waveforms
T
CLCH
T
CHCX
V
– 0.5
DD
V
IH1
T
CLCX
V
IL
0.45 V
T
CHCL
T
CLCL
Figure 26. External Clock Waveform
INPUTS
OUTPUTS
min
V
– 0.5
DD
0.2 V + 0.9
V
DD
IH
0.2 V – 0.1
V
max
DD
IL
0.45 V
Note:
During AC testing, all inputs are driven at V –0.5 V for a logic 1 and 0.45 V for a logic 0.
DD
Timing measurements are made on all outputs at V min for a logic 1 and V max for a logic 0.
IH
IL
Figure 27. AC Testing Input/Output Waveforms
V
+ 0.1 V
– 0.1 V
V
V
– 0.1 V
+ 0.1 V
LOAD
OH
OL
V
Timing Reference Points
LOAD
V
LOAD
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from
the loading V /V level occurs with I /I = ±20 mA.
OH OL
OL OH
Figure 28. Float Waveforms
47
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
