TSC87251G1A
(1)
LHLL
T
ALE
(1)
LLRL
(1)
RLRH
T
T
T
RHLH2
RD#/PSEN#
(1)
T
RLDV
T
RLAZ
(1)
T
RHDZ2
T
LHAX
(1)
T
AVLL
T
T
RHDX
LLAX
A7:0
P2
D7:0
Data In
(1)
AVRL
T
T
RHAX
(1)
T
AVDV1
(1)
T
AVDV2
P0/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 18. External Bus Cycle: Data Read (Page Mode)
ALE
WR#
(1)
T
LHLL
(1)
T
WLWH
T
WHLH
(1)
T
LHAX
T
QVWH
(1)
T
AVLL
T
LLAX
T
WHQX
A7:0
D7:0
P2
(1)
Data Out
T
AVWL1
(1)
T
T
WHAX
AVWL2
A15:8/A16/A17
P0/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 19. External Bus Cycle: DataWrite (Page Mode)
40
Rev. A – September 21, 1998