TSC87251G1A
11.3. AC Characteristics – SSLC: I2C Interface
Timings
2
Table 47. I C Interface AC Timing; V = 4.5 to 5.5 V, T = –40 to 85°C
DD
A
Symbol
Parameter
INPUT
OUTPUT
Min
Max
Min
4.0 µs
4.7 µs
4.0 µs
Max
(4)
(1)
THD; STA
Start condition hold time
SCL low time
14×TCLCL
16×TCLCL
14×TCLCL
(4)
(4)
(1)
(1)
TLOW
THIGH
SCL high time
(2)
TRC
SCL rise time
1 µs
–
(3)
TFC
SCL fall time
0.3 µs
0.3 µs
(4)
TSU; DAT1
TSU; DAT2
TSU; DAT3
THD; DAT
TSU; STA
TSU; STO
TBUF
Data set–up time
250 ns
20×TCLCL – TRD
(1)
SDA set–up time (before repeated START condition)
SDA set–up time (before STOP condition)
Data hold time
250 ns
1 µs
(4)
250 ns
8×TCLCL
(4)
0 ns
8×TCLCL
– TFC
(4)
(4)
(4)
(1)
Repeated START set–up time
STOP condition set–up time
Bus free time
14×TCLCL
14×TCLCL
14×TCLCL
4.7 µs
(1)
4.0 µs
(1)
4.7 µs
(2)
(3)
TRD
SDA rise time
1 µs
–
TFD
SDA fall time
0.3 µs
0.3 µs
Notes:
1. At 100 kbit/s. At other bit–rates this value is inversely proportional to the bit–rate of 100 kbit/s.
2. Determined by the external bus–line capacitance and the external bus–line pull–up resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3×TCLCL will be filtered out. Maximum capacitance on bus–lines SDA and
SCL= 400 pF.
4. TCLCL= T
= one oscillator clock period.
OSC
Waveforms
START or repeated START condition
Repeated START condition
STOP condition
START condition
T ;STA
SU
T
RD
SDA
(INPUT/OUTPUT)
0.7 V
0.3 V
DD
DD
T
BUF
T
FD
T
RC
T
FC
T ;STO
SU
SCL
0.7 V
0.3 V
DD
DD
(INPUT/OUTPUT)
T ;DAT3
SU
T ;STA
HD
T
LOW
T
HIGH
T ;DAT1
SU
T ;DAT
HD
T ;DAT2
SU
2
Figure 21. I C Waveforms
42
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
