TSC87251G1A
ALE
WR#
(1)
T
LHLL
(1)
T
WLWH
T
WHLH
(1)
LHAX
T
T
QVWH
(1)
AVLL
T
T
LLAX
T
WHQX
A7:0
D7:0
P0
(1)
Data Out
T
AVWL1
(1)
T
T
WHAX
AVWL2
A15:8/A16/A17
P2/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 44.
Figure 16. External Bus Cycle: DataWrite (Non–Page Mode)
Waveforms in Page Mode
ALE
(1)
T
LHLL
(1)
(1)
RLRH
T
LLRL
T
T
RHRL
T
RHLH1
(3)
RD#/PSEN#
(1)
T
RLDV
T
RLAZ
T
RHDZ1
(1)
T
LHAX
(1)
T
T
T
RHDX
AVLL
LLAX
A15:8
D7:0
D7:0
Instruction In
P2
Instruction In
(1)
AVRL
T
T
AXDX
(1)
T
AVDV1
T
RHAX
(1)
T
AVDV3
(1)
T
AVDV2
P0/A16/A17
A7:0/A16/A17
A7:0/A16/A17
(2)
(2)
Page Miss
Page hit
Notes:
1. The value of this parameter depends on wait states. See Table 44.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch) requires one state (2×T
); a page miss requires two
OSC
states (4×T
).
OSC
3. During a sequence of page hits, PSEN# toggles between each byte fetching.
Figure 17. External Bus Cycle: Code Fetch (Page Mode)
Rev. A – September 21, 1998
39
TEMIC [ TEMIC SEMICONDUCTORS ]
