TSC87251G1A
Table 44. Bus Cycles AC Timings; V = 4.5 to 5.5 V, T = –40 to 85°C
DD
A
16 MHz
FOSC Variable
Min Max
Symbol
Parameter
Unit
Min
63
Max
T
OSC
1/F
ns
OSC
(2)
T
ALE Pulse Width
53
T
T
T
T
T
T
T
–10
–20
–20
–18
–10
–18
–10
ns
LHLL
OSC
OSC
OSC
OSC
OSC
OSC
OSC
(2)
T
AVLL
Address Valid to ALE Low
43
ns
T
LLAX
Address hold after ALE Low
43
ns
(1)
(3)
T
RLRH
RD#/PSEN# Pulse Width
45
ns
T
RHRL
RD#/PSEN# High to RD#/PSEN# Low
WR# Pulse Width
53
ns
(3)
T
45
ns
WLWH
(1)
T
LLRL
ALE Low to RD#/PSEN# Low
ALE High to Address Hold
53
ns
(2)
T
LHAX
105
2×T
–20
ns
OSC
(1)
(3)
T
RD#/PSEN# Low to Valid Data
Data Hold After RD#/PSEN# High
Address Hold After RD#/PSEN# High
RD#/PSEN# Low to Address Float
Instruction Float After RD#/PSEN# High
Data Float After RD#/PSEN# High
RD#/PSEN# high to ALE High (Instruction)
RD#/PSEN# high to ALE High (Data)
WR# High to ALE High
43
T
–20
ns
RLDV
RHDX
RHAX
OSC
(1)
(1)
T
T
T
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
(1)
2
2
RLAZ
T
43
43
T
OSC
T
OSC
–20
–20
RHDZ1
RHDZ2
RHLH1
RHLH2
T
T
T
48
T
–15
OSC
173
173
3×T
3×T
–15
–15
OSC
T
ns
WHLH
OSC
(2)(3)
T
Address (P0) Valid to Valid Data In
Address (P2) Valid to Valid Data In
Address (P0) Valid to Valid Instruction In
Data Hold after Address Hold
Address Valid to RD# Low
190
273
128
3×T
4×T
3×T
–60
ns
AVDV1
OSC
OSC
OSC
(2)(3)
T
–60
–60
ns
AVDV2
T
ns
AVDV3
T
0
0
ns
AXDX
(1)
(2)
T
AVRL
101
101
158
43
2×T
2×T
3×T
–24
–24
–30
ns
OSC
OSC
OSC
(2)
(2)
T
Address (P0) Valid to WR# Low
Address (P2) Valid to WR# Low
Data Hold after WR# High
ns
AVWL1
T
ns
AVWL2
T
T
T
–20
ns
WHQX
QVWH
WHAX
OSC
OSC
(3)
T
T
Data Valid to WR# High
38
–25
–20
ns
WR# High to Address Hold
105
2×T
ns
OSC
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2×T
OSC.
3. If a wait state is added by extending RD#/PSEN#/WR#, add 2×T
.
OSC
37
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
