TSC87251G1A
CONFIG1
Configuration Byte 1
7
–
6
–
5
–
4
3
2
–
1
–
0
INTR
WSB
EMAP#
Bit
Number
Bit
Mnemonic
Description
Reserved
Set this bit when writing to CONFIG1.
7
6
5
–
Reserved
Set this bit when writing to CONFIG1.
–
–
Reserved
Set this bit when writing to CONFIG1.
(1)
Interrupt Mode bit
Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the PSW1
register).
4
3
INTR
WSB
Wait State B bit
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
Reserved
Set this bit when writing to CONFIG1.
2
1
–
–
Reserved
Set this bit when writing to CONFIG1.
On–Chip Code Memory Map bit
Clear to map the upper 8 Kbytes of on–chip code memory (at FF:2000h–FF:3FFFh) to the data space (at
00:E000h–00:FFFFh).
0
EMAP#
Set not to map the upper 8 Kbytes of on–chip code memory (at FF:2000h–FF:3FFFh) to the data space.
Note:
1. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used with code
executing outside region FF:.
Figure 7. Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
RD1
RD0
P1.7
P3.7/RD#
PSEN#
WR#
External Memory
0
0
A17
A16
Read signal for all external Write signal for all external
memory locations memory locations
256 Kbytes
0
1
1
1
0
1
I/O pin
I/O pin
A16
Read signal for all external Write signal for all external
memory locations memory locations
128 Kbytes
64 Kbytes
I/O pin
Read signal for all external Write signal for all external
memory locations memory locations
(1)
I/O pin Read signal for regions 00: Read signal for regions FE: Write signal for all external
and 01: and FF: memory locations
2 × 64 Kbytes
Note:
1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.
14
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
