TSC87251G1A
6.4. Configuration Bytes
The TSC87251G1A derivatives provide user design flexibility by configuring certain operating features at device reset.
These features fall into the following categories:
D external memory interface (page mode, address bits, programmed wait states and the address range for RD#,
WR#, and PSEN#)
D source mode/binary mode opcodes
D selection of bytes stored on the stack by an interrupt
D mapping of the upper portion of on–chip code memory to region 00:
Two user configuration bytes CONFIG0 (see Figure 6) and CONFIG1 (see Figure 7) provide the information.
For TSC87251G1A devices, configuration information is stored in on–chip separate memory (see paragraph 8.
“EPROM Programming”). Whatever the EA# level, the configuration information is retrieved from this on–chip
memory.
CONFIG0
Configuration Byte 0
7
–
6
–
5
4
3
2
1
0
WSA
XALE#
RD1
RD0
PAGE#
SRC
Bit
Number
Bit
Mnemonic
Description
Reserved
Set this bit when writing to CONFIG0.
7
6
–
Reserved
–
Set this bit when writing to CONFIG0.
Wait State A bits
5
4
WSA
Clear to generate one wait state for all memory region except 01:.
Set for no wait states for all memory region except 01:.
Extend ALE bit
Clear to extend the duration of the ALE pulse from T
XALE#
to 3×T
OSC.
OSC
Set to minimize the duration of the ALE pulse to 1×T
.
OSC
3
2
RD1
RD0
Memory Signal Select bits
Specify a 18–bit, 17–bit or 16–bit external address bus and the usage of RD#, WR# and PSEN# signals
(see Table 13).
Page Mode Select bit
1
0
PAGE#
SRC
Clear to select the faster page mode with A15:8/D7:0 on Port 2 and A7:0 on Port 0.
Set to select the non–page mode with A15:8 on Port 2 and A7:0/D7:0 on Port 0.
(1)
Source Mode/Binary Mode Select bit
Clear to select the binary mode.
Set to select the source mode.
Note:
1. This selection provides compatibility with the standard 80C51 hardware which is multiplexing the address LSB and the data on Port 0.
Figure 6. Configuration Byte 0
13
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
