TS80C52X2
6.6 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give and indication if an interrupt occured during normal operation or
during and Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The over way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the
hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
6.7 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 9., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
V
can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
CC
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before V
CC
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 10.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C52X2 into power-down mode.
INT0
INT1
XTAL1
Active phase
Power-down phase
Oscillator restart phase
Active phase
Figure 10. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.
28
Rev. B - Jan. 25, 1999
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
