TS80C52X2
Table 12. IP Register
IP - Interrupt Priority Register (B8h)
7
-
6
-
5
4
3
2
1
0
PT2
PS
PT1
PX1
PT0
PX0
Bit
Number
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
6
5
4
3
2
1
0
-
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 overflow interrupt Priority bit
PT2
PS
Refer to PT2H for priority level.
Serial port Priority bit
Refer to PSH for priority level.
Timer 1 overflow interrupt Priority bit
PT1
PX1
PT0
PX0
Refer to PT1H for priority level.
External interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = XX00 0000b
Bit addressable
26
Rev. B - Jan. 25, 1999
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
