TS80C52X2
Table 13. IPH Register
IPH - Interrupt Priority High Register (B7h)
7
-
6
-
5
4
3
2
1
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
6
-
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 overflow interrupt Priority High bit
PT2H
PT2
0
1
0
1
Priority Level
Lowest
0
0
1
1
5
4
3
2
1
0
PT2H
Highest
Serial port Priority High bit
PSH
PS
0
1
0
1
Priority Level
Lowest
0
0
1
1
PSH
Highest
Timer 1 overflow interrupt Priority High bit
PT1H
PT1
0
1
0
1
Priority Level
Lowest
0
0
1
1
PT1H
PX1H
PT0H
PX0H
Highest
External interrupt 1 Priority High bit
PX1H
PX1
Priority Level
Lowest
0
0
1
1
0
1
0
1
Highest
Timer 0 overflow interrupt Priority High bit
PT0H
PT0
0
1
0
1
Priority Level
Lowest
0
0
1
1
Highest
External interrupt 0 Priority High bit
PX0H
PX0
Priority Level
Lowest
0
0
1
1
0
1
0
1
Highest
Reset Value = XX00 0000b
Not bit addressable
Rev. B - Jan. 25, 1999
27
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
