TS80C52X2
Table 10. Priority Level Bit Values
IP.x
IPH.x
Interrupt Level Priority
0
0
1
1
0
1
0
1
0 (Lowest)
1
2
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 11. IE Register
IE - Interrupt Enable Register (A8h)
7
6
-
5
4
3
2
1
0
EA
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
7
EA
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
5
-
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
ET2
Serial port Enable bit
4
3
2
1
0
ES
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
ET1
EX1
ET0
EX0
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0X00 0000b
Bit addressable
Rev. B - Jan. 25, 1999
25
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
