ICM-20690
12.19 REGISTER 36 – I2C MASTER CONTROL
Register Name: I2C_MST_CTRL
Register Type: READ/WRITE
Register Address: 36 (Decimal); 24 (Hex)
BIT
[7]
NAME
FUNCTION
1 – Enables multi-master capability
0 – Function is disabled
Reserved
MULT_MST_EN
-
[6:5]
This bit controls the I2C master’s transition from one slave read to the next slave
read
1 – There is a stop between reads
0 – There is a restart between reads
Sets I2C master clock according to the table below
[4]
I2C_MST_P_NSR
I2C_MST_CLK
[3:0]
I2C_MST_CLK[3:0]
Slowest Frequency (kHz)
Duty Cycle
0
1
341
341
42%
50%
2
315
38%
3
315
46%
4
293
43%
5
293
50%
6
273
40%
7
273
47%
8
256
38%
9
Invalid
Invalid
Invalid
410
410
372
Invalid
Invalid
Invalid
40%
40%
45%
10
11
12
13
14
15
372
45%
12.20 REGISTER 37 – I2C SLAVE 0 PHYSICAL ADDRESS
Register Name: I2C_SLV0_ADDR
Register Type: READ/WRITE
Register Address: 37 (Decimal); 25 (Hex)
BIT
[7]
NAME
FUNCTION
1 – Transfer is a read
0 – Transfer is a write
Physical address of I2C slave 0
I2C_SLV0_RNW
I2C_ID_0
[6:0]
Page 52 of 76
Document Number: DS-000178
Revision: 1.0
TDK [ TDK ELECTRONICS ]
