ICM-20690
11.1 REGISTERS SPECIFIC TO SECONDARY INTERFACE IN OIS MODE
The following registers are accessible from the secondary interface in OIS mode only. OIS controller should only read this data in SPI
burst mode to avoid OIS sensor data update during reading. SPI single byte read mode should not be used.
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00
01
02
03
00
01
02
03
ACCEL_XOUT_OIS_H
ACCEL_XOUT_OIS_L
ACCEL_YOUT_OIS_H
ACCEL_YOUT_OIS_L
READ
READ
READ
READ
ACCEL_XOUT_OIS[15:8]
ACCEL_XOUT_OIS[7:0]
ACCEL_YOUT_OIS[15:8]
ACCEL_YOUT_OIS[7:0]
04
05
06
07
08
09
0A
0B
0C
0D
04
05
06
07
08
09
10
11
12
13
ACCEL_ZOUT_OIS_H
ACCEL_ZOUT_OIS_L
TEMP_OUT_OIS_H
TEMP_OUT_OIS_L
GYRO_XOUT_OIS_H
GYRO_XOUT_OIS_L
GYRO_YOUT_OIS_H
GYRO_YOUT_OIS_L
GYRO_ZOUT_OIS_H
GYRO_ZOUT_OIS_L
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
ACCEL_ZOUT_OIS[15:8]
ACCEL_ZOUT_OIS[7:0]
TEMP_OUT_OIS[15:8]
TEMP_OUT_OIS[7:0]
GYRO_XOUT_OIS[15:8]
GYRO_XOUT_OIS[7:0]
GYRO_YOUT_OIS[15:8]
GYRO_YOUT_OIS[7:0]
GYRO_ZOUT_OIS[15:8]
GYRO_ZOUT_OIS[7:0]
Table 17. Registers Specific to Secondary Interface in OIS Mode
Page 43 of 76
Document Number: DS-000178
Revision: 1.0
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