ICM-20690
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
ACCEL_INTEL_CTRL
USER_CTRL
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
READ/
WRITE
ACCEL_INTE
L_EN
ACCEL_INTEL
_MODE
WOM_INT_
MODE
69
6A
6B
6C
70
105
106
107
108
112
ACCEL_FCHOICE_OIS_B
-
READ/
WRITE
FIFO
_RST
SIG_COND
_RST
-
FIFO_EN
SLEEP
-
I2C_MST_EN
I2C_IF_DIS
I2C_MST_RST
CLKSEL[2:0]
STBY_YG
READ/
WRITE
DEVICE_RES
ET
GYRO_
STANDBY
PWR_MGMT_1
PWR_MGMT_2
OIS_ENABLE
CYCLE
TEMP_DIS
STBY_ZA
READ/
WRITE
LP_DIS
STBY_XA
STBY_YA
STBY_XG
STBY_ZG
-
READ/
WRITE
-
OIS_ENABLE
72
73
114
115
FIFO_COUNTH
FIFO_COUNTL
READ
READ
FIFO_COUNT[15:8]
FIFO_COUNT[7:0]
FIFO_DATA[7:0]
WHOAMI[7:0]
READ/
WRITE
74
75
77
116
117
119
FIFO_R_W
WHO_AM_I
XA_OFFSET_H
READ
READ/
WRITE
XA_OFFS[14:7]
READ/
WRITE
78
7A
7B
7D
7E
120
122
123
125
126
XA_OFFSET_L
YA_OFFSET_H
YA_OFFSET_L
ZA_OFFSET_H
ZA_OFFSET_L
XA_OFFS[6:0]
-
-
-
READ/
WRITE
YA_OFFS[14:7]
READ/
WRITE
YA_OFFS[6:0]
READ/
WRITE
ZA_OFFS[14:7]
READ/
WRITE
ZA_OFFS[6:0]
Table 16. ICM-20690 Register Map
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
The reset value is 0x00 for all registers other than the registers below; also, the self-test registers contain pre-programmed values
and will not be 0x00 after reset.
Registers 00 – 02: Trim values
Registers 13 – 15: Trim values
Register 105 ACCEL_INTEL_CTRL value: 0x10
Register 107 Power Management 1 value: 0x41
Register 117 WHO_AM_I value: 0x20
Registers 119, 120, 122, 123, 125, 126: Trim values
Page 42 of 76
Document Number: DS-000178
Revision: 1.0
TDK [ TDK ELECTRONICS ]
