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ICM-20690 参数 Datasheet PDF下载

ICM-20690图片预览
型号: ICM-20690
PDF下载: 下载PDF文件 查看货源
内容描述: [IMU (惯性测量设备)]
分类和应用:
文件页数/大小: 76 页 / 1486 K
品牌: TDK [ TDK ELECTRONICS ]
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ICM-20690  
6 DIGITAL INTERFACE  
6.1 I2C AND SPI SERIAL INTERFACES  
The internal registers and memory of the ICM-20690 can be accessed using either I2C at 400 kHz or SPI at 10 MHz. SPI operates in  
four-wire mode.  
Pin Number  
Pin Name  
Pin Description  
Application Processor (AP) Interface: AP I2C slave address LSB (AP_AD0); AP SPI serial  
data output (AP_SDO)  
1
AP_AD0 / AP_SDO  
12  
13  
14  
AP_CS  
AP SPI Chip select (SPI mode only)  
AP_SCL / AP_SCLK  
AP_SDA / AP_SDI  
AP I2C serial clock (AP_SCL); AP SPI serial clock (AP_SCLK)  
AP I2C serial data (AP_SDA); AP SPI serial data input (AP_SDI)  
Table 14. Serial Interface  
Note:  
To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit.  
Setting this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write”  
in Section 6.3.  
For further information regarding the I2C_IF_DIS bit, please refer to sections 11 and 12 of this document.  
6.2 I2C INTERFACE  
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-  
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the  
slave address on the bus, and the slave device with the matching address acknowledges the master.  
The ICM-20690 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA  
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.  
The slave address of the ICM-20690 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level  
on pin AD0. This allows two ICM-20690s to be connected to the same I2C bus. When used in this configuration, the address of one of  
the devices should be b1101000 (pin AD0 is logic low) and the address of the other should be b1101001 (pin AD0 is logic high).  
Page 27 of 76  
Document Number: DS-000178  
Revision: 1.0  
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