ICM-20690
6.5 SPI INTERFACE
The ICM-20690 support 4-wire SPI for host interface and 3-wire SPI for the OIS interface. 4-wire SPI is a synchronous serial interface
that uses two control lines and two data lines. 3-wire SPI is a synchronous serial interface that uses two control lines and one data
line. The ICM-20690 always operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO) and the Serial Data Input (SDI) for 4-wire SPI
(or Serial Data IO (SDOI) for 3-wire SPI) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (nCS)
line from the master.
nCS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one nCS line is active at a time,
ensuring that only one slave is selected at any given time. The nCS lines of the non-selected slave devices are held high, causing their
SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 10 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiple-
byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
LSB
D7
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
SCLK
SDI
SPI Master
SPI Slave 1
SDO
nCS
CS1
CS2
SCLK
SDI
SDO
nCS
SPI Slave 2
Figure 11. Typical SPI Master/Slave Configuration
Page 31 of 76
Document Number: DS-000178
Revision: 1.0
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