78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
LEGEND
TYPE DESCRIPTION
TYPE DESCRIPTION
R/W Read or Write
R/O
Read only
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Register Control Enable:
0 : Pin selection overrides register settings
1 : Device is controlled via register set.
7
REGEN
R/W
0
NOTE: Pin 15 (ENDEC) must be tied low when REGEN is enabled.
Line Speed Selection: Selects the line speed of all channels as well as
the input clock frequency at the CKREF pin.
[DS3 E3] = 00 : STS-1 (51.840MHz)
01 : E3 (34.368MHz)
6
5
DS3
E3
R/W
R/W
X
X
10 : DS3 (44.736MHz)
11 : STS-1 (51.840MHz)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset.
Encoder/Decoder Disable:
0 : selects NRZ digital data interface
1 : selects AMI digital data interface
4
ENDEC
R/W
0
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDEC pin
selection prevails.
RCLK Polarity Selection:
3
2
RCLKP
TCLKP
R/W
R/W
0
0
0 : Receive Data clocked out on the falling-edge of RCLK
1 : Receive Data clocked out on the rising-edge of RCLK
TCLK Polarity Selection:
0 : Transmit Data clocked in on the rising-edge of TCLK
1 : Transmit Data clocked in on the falling-edge of TCLK
1
0
RSVD
SRST
R/O
R/W
X
0
Reserved
Register Soft-Reset: When this bit is set, all registers are reset to their
default values. Also resets Jitter Attenuator to “centered” states. This
register bit is self-clearing.
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