78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
SIGNAL DETECT
On the transmit side, when the ENDEC is enabled,
NRZ input data is encoded to Positive and Negative
AMI logic data following the B3ZS (for DS3/STS-1)
or HDB3 (for E3) substitution codes. The NRZ data
is input to the TPOS pin as shown below:
When the received signal is below a minimum
threshold, the corresponding LOS signal (bit) is
asserted. A time delay is provided before this output
is active so that transient interruptions do not cause
false indications. The LOS signal can also be used
to trigger an interrupt on the INTRx pin when serial
interface control is not available. This is controlled
by setting the RXER bit in the Interrupt Control
Register (INTC).
ENDEC
bit/pin
TPOSx
TNEGx
0 / L
NRZ data
‘Don’t Care’
Note: In DS3 or STS-1 mode, when LBO is not
enabled, the transmitters have to be properly
terminated to ensure reliable LOS detection. If a
transmitter is not terminated, the resultant 2x signal
is large enough to couple to the neighboring
receivers through the ESD diodes, causing false
Signal Detect indication.
1 / H
Positive AMI
Negative AMI
TRANSMITTER OPERATION
Both transmitters are enabled by their corresponding
TXEN bit. When enabled, each transmitter accepts
logic level clock (TCLKx), positive data (TPOSx) and
negative data (TNEGx) signals and generates
current pulses on the LOUTPx and LOUTNx pins.
When properly connected to a 1:2CT center-tapped
transformer, an AMI pulse is generated which can
B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION
DETECT
The 78P2342JAT includes a selectable B3ZS/HDB3
Encoder/Decoder (ENDEC). The ENDEC function
can be enabled or disabled through pin selection or
register setting. When the ENDEC is enabled, the
decoder generates a composite NRZ logic data
stream following the B3ZS (for DS3/STS-1) or HDB3
(for E3) substitution codes via the RPOS pin as
shown below:
drive a 75
Ω
coaxial cable.
When the recommended transformer is used and
when DS3 mode is selected, the transmitted pulse
shape at the end of the 75
Ω
terminated cable of 0 to
450 feet will fit the DS3 template in ANSI T1.102-
1993 and Telcordia GR-499-CORE standard
documents. For STS-1 applications, the transmitted
pulse for a short cable meets the requirements of
Telcordia GR-253-CORE.
ENDEC
bit/pin
RPOSx
RNEGx
For E3 applications, the transmitted pulse for a short
cable meets the requirements of ITU-T G.703.
Receive Line Code
Violation Indicator
0 / L
NRZ data
In either DS3 and STS-1 modes, the LBOx pin or
LBO bit should be set high for short cable (< 225 ft),
and should be set low for long cable (> 225 ft). The
LBO settings are ignored in E3 mode.
1 / H
Positive AMI
Negative AMI
The decoder also detects Receive Line Code
Violations (RLCV) and outputs a pulse via the
RNEG pin. Three different classes of line code
violations are detected.
RCLK/TCLK POLARITY REVERSAL
To simplify the interface with various framer circuitry,
TCLK polarity can be internally inverted by setting
the TCLKP bit, and RCLK polarity can be inverted
by setting the RCLKP bit. Both bits are located in
the Master Control Register (MSCR).
1) Too many zeros:
More than two (three)
consecutive zeros in B3ZS (HDB3) mode.
2) Not enough zeros between bipolar pulse (B)
and bipolar violation pulse (V): (B,V) for B3ZS.
(B,V) or (B,0,V) for HDB3.
REMOTE (DIGITAL) LOOPBACK
3) Code violation: Even number of bipolar pulses
(B) detected between bipolar violation pulses
(V).
When the Register Control bit, REGEN, is disabled
and the LPBKx pin is floating; or when the Register
Control bit, REGEN, is enabled and the RLBK bit is
set, RCLKx, RNEGx, and RPOSx outputs are
internally looped back to the TCLKx, TNEGx, and
TPOSx inputs respectively.
- 4 -
TDK [ TDK ELECTRONICS ]
