78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS N-3: JITTER ATTENUATOR CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Jitter Attenuator Enable:
0 : Disables jitter attenuation function
1 : Enables jitter attenuation function
7
JAEN
R/W
X
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
Jitter Attenuation Selection:
0 : Jitter Attenuator on the receive path
1 : Jitter Attenuator on the transmit path
6
JASL
R/W
X
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
Jitter Attenuator Local Loopback Enable:
0 : Normal Operation
1 : TCLKx, TPOSx, TNEGx connected to JAT input and
5
4
JLBK
R/W
R/W
0
0
RCLKx, RPOSx, RNEGx connected to JAT output
NOTE: If both RLBK and JLBK bits are set, RLBK mode takes priority.
Reserved. Must be set to zero.
RSVD
FIFO Elastic Store Pointer Selection:
00 : Pass-through
ESP
[1:0]
3:2
1
R/W
R/W
11
0
01 : 8 UI
10 : 16 UI
11 : 32 UI
RSVD
Reserved. Must be set to zero.
Jitter Attenuator Bandwidth Selection:
0 : Low bandwidth
1 : High bandwidth
(see JAT Bandwidth Selection Table on page 5)
JABW
0
R/W
X
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset. If the state of the MSL0 pin
selects E3 or DS3 mode, the default value of JABW is ‘0’. If the state of
the MSL0 pin selects STS1 mode, the default value of JABW is ‘1’.
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