78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
CONTROL AND STATUS PINS (continued)
Line Build-Out:
Low = Used with 225ft or more of cable.
High = Used with less than 225ft of cable.
5, 6
CIT
LBOx
Float = Disable and power down transmitter. [TXEN=0; PDTX=1]
NOTE: Relevant only when the REGEN bit is ‘0’. Pin state sampled
approximately once every 0.5ms.
Loopback Enable:
Low = Normal Operation
High = Local Loopback. Transmitter looped back to Receiver
10, 11
64, 63
CIT
CO
LPBKx
INTRx
Float = Remote Loopback. Receiver looped back to Transmitter
NOTE: Relevant only when the REGEN bit is ‘0’. Pin state sampled
approximately once every 0.5ms.
Interrupt Flag:
This pin is normally high when the INPOL bit is ‘0’ (default), and
normally low when the INPOL bit is ‘1’. When an interrupt event
occurs (as defined in the Interrupt Control Register description), the
respective INTRx pin will change state.
SERIAL-PORT PINS
NAME
PIN
65
TYPE
CI
DESCRIPTION
Chip Select: High during write and read operations. Low disables the
serial port. While CS is low, SDO remains in high impedance state,
and SDI and SCK activities are ignored.
CS
SCK
SDI
66
CIS
CI
Serial Clock: Controls the timing of SDI and SDO.
Serial Data Input: Inputs mode and address information. Also inputs
register data during a Write operation. Both address and data are input
least significant bit first.
68
Serial Data Output: Outputs register information during a Read
operation. Data is output least significant bit first.
SDO
67
COZ
POWER AND GROUND PINS
It is recommended that all supply pins be connected to a single power supply plane and all ground pins be
connected to a single ground plane.
NAME
PIN
TYPE
DESCRIPTION
1, 2, 3, 4, 17,
59, 72, 73,
74, 75
VCC
S
Analog Power Supply
18, 60, 78,
81, 84, 87,
91, 94, 97,
100
GND
S
Analog Ground
16, 22, 30,
38, 46, 54,
55, 58
VCCD
GNDD
S
S
Digital Power Supply
Digital Ground
- 15 -
9, 21, 26, 34,
42, 50, 56, 69
TDK [ TDK ELECTRONICS ]
