78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
RECEIVER PINS
NAME
PIN
TYPE
DESCRIPTION
Reference Clock Input: This clock should be from a clean source
(± 20 ppm) and represents the line-rate frequency as follows:
57
CIS
CKREF
E3 : 34.368 MHz
DS3: 44.736 MHz
STS-1: 51.840 MHz
Receive Clock: Recovered receive clock.
27, 35
28, 36
CO
RCLKx
RNEGx
Note: During LOS conditions, RCLKx will continue to output a line
rate clock
Receive Negative Data: When ENDEC bit =’1’, this pin indicates
reception of a negative AMI pulse on the coax. When ENDEC bit =’0’,
this pin outputs a one when a receive line code violation is detected.
Receive Positive Data/NRZ Data: When ENDEC bit =’1’, this pin
indicates reception of a positive AMI pulse on the coax cable. When
ENDEC bit =’0’, it outputs decoded NRZ data.
CO
CO
29, 37
96, 90
RPOSx
LINPx
Line In: Differential AMI Inputs. Should be 1:1 transformer-coupled
and terminated with a shunt resistor. See APPLICATION
INFORMATION section for more info.
A
95, 89
LINNx
CONTROL AND STATUS PINS
NAME
PIN
TYPE
DESCRIPTION
Data-Rate Mode Selection:
Low = E3 mode
High = DS3 mode
19
CIT
MSL0
Float = STS-1 mode
NOTE: Pin state is latched-in on rising-edge of POR signal
Jitter Attenuator Mode Selection:
Low = JAT in Receive path
High = JAT in Transmit path
Float = JAT is bypassed
20
CIT
MSL1
NOTE: Pin state is latched-in on rising-edge of POR signal
Chip Reset (active-low):
14
15
A
POR
Forces hardware reset on device. See description on Internal Power-
on Reset for complete use of this pin.
ENDEC Enable (active-low):
Set high to disable internal ENDEC function.
CID
ENDEC
NOTE: Relevant only when the REGEN bit is ‘0’. Pin must be held
low when the REGEN bit is set.
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