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TCS3414 参数 Datasheet PDF下载

TCS3414图片预览
型号: TCS3414
PDF下载: 下载PDF文件 查看货源
内容描述: 数字色彩传感器 [DIGITAL COLOR SENSORS]
分类和应用: 传感器
文件页数/大小: 40 页 / 348 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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TCS3404, TCS3414  
DIGITAL COLOR SENSORS  
TAOS137A − APRIL 2011  
Gain Register (07h)  
The Gain register provides a common gain control adjustment for all four parallel ADC output channels. Two  
gain bits [5:4] in the Gain Register allow the relative gain to be adjusted from 1× to 64× in 4× increments. The  
advantage of the gain adjust is to extend the dynamic range of the light input up to a factor of 64× before analog  
or digital saturation occurs. If analog saturation has occurred, lowering the gain sensitivity will likely prevent  
analog saturation especially when the integration time is relatively short. For longer integration times, the 16-bit  
output could be in digital saturation (64K). If lowering the gain to 1× does not prevent digital saturation from  
occurring, the use of PRESCALER can be useful.  
The PRESCALER is 3 bits [2:0] in the gain register that divides down the output count (i.e. shifts the LSB of the  
count value to the right). The PRESCALER adjustment range is divide by 1 to 64 in multiples of 2.  
The most sensitive gain setting of the device would be when GAIN is set to 11b (64×), and PRESCALER is set  
to 000b (divide by 1). The least sensitive part setting would be GAIN 00 (1×) and PRESCALER 110 (divide by  
64). If the part continues to be in digital saturation at the least sensitive setting, the integration time can be  
lowered (see Timing Register section).  
Table 9. Gain Register  
7
Resv  
0
6
Resv  
0
5
0
4
0
3
Resv  
0
2
1
0
0
GAIN  
07h  
GAIN  
PRESCALER  
0
Reset Value:  
0
FIELD  
BITS  
DESCRIPTION  
Resv  
7:6  
5:4  
3
Reserved. Write as 0.  
Analog Gain Control. This field switches the common analog gain of the four ADC channels. Four gain  
modes are provided:  
FIELD VALUE  
GAIN  
00  
1×  
4×  
16×  
64×  
GAIN  
Resv  
01  
10  
11  
Reserved. Write as 0.  
Prescaler. This field controls a 6-bit digital prescaler and divider. The prescaler reduces the sensitivity  
of each ADC integrator as shown in the table below:  
FIELD VALUE  
PRESCALER MODE  
000  
001  
010  
011  
100  
101  
110  
111  
Divide by 1.  
Divide by 2.  
Divide by 4.  
Divide by 8.  
Divide by 16.  
Divide by 32.  
Divide by 64.  
Not used.  
PRESCALER  
2:0  
Copyright E 2011, TAOS Inc.  
The LUMENOLOGY r Company  
r
r
www.taosinc.com  
19  
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