TCS3404, TCS3414
DIGITAL COLOR SENSORS
TAOS137A − APRIL 2011
Interrupt Threshold Register (08h − 0Bh)
The interrupt threshold registers store the values to be used as the high and low trigger points for the comparison
function for interrupt generation. The high and low bytes from each set of registers are combined to form a 16-bit
threshold value. If the value generated by the Interrupt Source Register (03h) converges below or equal to the
low threshold specified, an interrupt is asserted on the interrupt pin. If the value generated by Interrupt Source
Register (03h) converges above the high threshold specified, an interrupt is asserted on the interrupt pin.
Registers LOW_THRESH_LOW_BYTE and LOW_THRESH_HIGH_BYTE provide the low byte and high byte,
respectively, of the lower interrupt threshold. Registers HIGH_THRESH_LOW_BYTE and
HIGH_THRESH_HIGH_BYTE provide the low and high bytes, respectively, of the upper interrupt threshold.
The interrupt threshold registers default to 00h on power up.
Table 10. Interrupt Threshold Register
REGISTER
ADDRESS
08h
BITS
7:0
DESCRIPTION
LOW_THRESH_LOW_BYTE
LOW_THRESH_HIGH_BYTE
HIGH_THRESH_LOW_BYTE
HIGH_THRESH_HIGH_BYTE
ADC interrupt source lower byte of the low threshold.
ADC interrupt source upper byte of the low threshold.
ADC interrupt source lower byte of the high threshold.
ADC interrupt source upper byte of the high threshold.
09h
7:0
0Ah
7:0
0Bh
7:0
NOTES: 1. The Interrupt Source Register (03h) selects which ADC channel to generate an interrupt and should correspond to the threshold
setting. Both registers should be configured appropriately when setting up an interrupt service routine.
2. Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the SMBus Send Byte
protocol should not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would
be interpreted as the COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt
threshold information as desired. The Write Word protocol should be used to write byte-paired registers. For example, the
LOW_THRESH_LOW_BYTE and LOW_THRESH_HIGH_BYTE registers (as well as the HIGH_THRESH_LOW_BYTE and
HIGH_THRESH_HIGH_BYTE registers) can be written together to set the 16-bit ADC value in a single transaction.
ADC Channel Data Registers (10h − 17h)
The ADC channel data are expressed as 16-bit values spread across four registers. The channel low and high
provide the lower and upper bytes respectively for each ADC channel data registers. Each DATALOW and
DATAHIGH register is identified below as 1, 2, 3, or 4. All channel data registers are read-only and default to
00h on power up.
Table 11. ADC Channel Data Registers
REGISTER
GREEN_LOW
GREEN_HIGH
RED_LOW
ADDRESS
10h
BITS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
DESCRIPTION
ADC channel 1 lower byte
11h
ADC channel 1 upper byte
ADC channel 2 lower byte
ADC channel 2 upper byte
ADC channel 3 lower byte
ADC channel 3 upper byte
ADC channel 4 lower byte
ADC channel 4 upper byte
12h
RED_HIGH
13h
BLUE_LOW
BLUE_HIGH
CLEAR_LOW
CLEAR_HIGH
14h
15h
16h
17h
The upper byte data registers can only be read following a read to the corresponding lower byte register. When
the lower byte register is read the upper eight bits are strobed into a shadow register, which is read by a
subsequent read to the upper byte. The upper register will therefore read the correct value even if additional
ADC integration cycles complete between the reading of the lower and upper registers.
NOTE: The SMBus Read Word protocol can be used to read byte-paired registers. For example, the DATA1LOW and DATA1HIGH registers (as
well as the other three individual register pairs) may be read together to obtain the 16-bit ADC value in a single transaction.
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
r
r
20
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