DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
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DS90UB914Q Deserializer Pin Descriptions (continued)
Pin Name
Pin No.
I/O, Type
Description
Device mode select pin
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. The MODE pin on the Deserializer
can be used to configure the Serializer and Deserializer to work in different input
PCLK range. See details in Table 2.
12– bit low frequency mode – (10- 50 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 12 bits DATA+2 SYNC.
Input PCLK range is from 10MHz to 50MHz.
12– bit high frequency mode – (15-75 MHz operation): In this mode, the Serializer
and Deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK range is from
15MHz to 75MHz.
Input, LVCMOS
w/ pull up
MODE
37
10–bit mode– (20–100 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 10 bits DATA + 2
SYNC. Input PCLK frequency can range from20 MHz to 100MHz.
Please refer to Table 6 in the Applications Information section on how to configure the
MODE pin on the Deserializer.
The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C device
address. Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 8
Input pin to select the Slave Device Address.
IDx[0:1]
35,34
Input, analog
Input is connect to external resistor divider to set programmable Device ID address
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Sleep (power down mode). When the Deserializer is in
Sleep, programmed control register data are NOT retained and reset to default
values.
Input, LVCMOS
w/ pull down
PDB
30
LOCK Status Output Pin.
Output,
LVCMOS
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
LOCK
48
6
Input
LVCMOS w/
pulldown
BIST Enable pin
BISTEN=H, BIST Mode Enabled
BISTEN=L, BIST Mode is disabled
BISTEN
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
Output,
LVCOMS
PASS
47
PASS = L, one or more errors were detected in the received payload.
See Built In Self Test section for more information. Leave Open if unused. Route to
test point (pad) recommended.
Input
LVCMOS w/
pulldown
Output Enable Input
Refer to Table 9
OEN
5
4
Input
LVCMOS w/
pulldown
Output Sleep State Select Pin
Refer to Table 9
OSS_SEL
MUX Select line
Input
SEL = L, RIN0+/- input. This selects input A as the active channel on the Deserializer.
SEL = H, RIN1+/- input. This selects input B as the active channel on the
Deserializer.
SEL
46
LVCMOS w/
pulldown
FPD–Link III INTERFACE
Input/Output,
CML
Non-Inverting Differential input, bidirectional control channel. The IO must be AC
coupled with a 100 nF capacitor
RIN0+
RIN0-
RIN1+
RIN1-
41
Input/Output,
CML
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 100 nF capacitor
42
32
33
Input/Output,
CML
Non-Inverting Differential input, bidirectional control channel. The IO must be AC
coupled with a 100 nF capacitor
Input/Output,
CML
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 100 nF capacitor
RES
43,44
38,39
—
Reserved. This pin must always be tied low
CMLOUTP/N
Route to test point or leave open if unused
POWER AND GROUND
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDIO1/2/3 29, 20, 7
Power, Digital
6
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