SNLS420B – JULY 2012 – REVISED APRIL 2013
Typical Application Diagram
Parallel
Data In
10 or 12
FPD-Link III
Parallel
Data Out
10 or 12
2
2
Megapixel
Imager/Sensor
HSYNC,
VSYNC
DS90UB913Q
DS90UB914Q
4
GPO
2
Bidirectional
Control Bus
Bidirectional
Control Channel
Serializer
Deserializer
HSYNC,
VSYNC
4
GPIO
2
Bidirectional
Control Bus
DSP, FPGA/
µ-Processor/
ECU
Figure 1. Typical Application Circuit
Block Diagrams
10
or
12
10 or
12
Serializer
Encoder
DIN
HSYNC
VSYNC
GPO[3:0]
DOUT-
PCLK
PLL
Clock
Gen
2:1
RIN0-
RIN1+
CDR
RIN1-
PDB
Timing and
Control
PDB
BISTEN
OEN
Timing and
Control
Clock
Gen
Adaptive Eq.
Output Latch
Input Latch
Deserializer
Decoder
R
T
R
T
DOUT+
RIN0+ R
T
R
T
ROUT
HSYNC
VSYNC
4
4
GPIO[3:0]
PCLK
LOCK
PASS
Decoder
Encoder
I2C Controller
FIFO
SEL
I2C
Controller
SDA
SCL
IDx[0]
IDx[1]
Decoder
SCL
ID[x]
MODE
MODE
DS90UB913Q - SERIALIZER
DS90UB914Q - DESERIALIZER
Figure 2. Block Diagram
DS90UB913Q
Serializer
Camera Data
10 or 12
DOUT+
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
PCLK
DS90UB914Q
Deserializer
FPD-Link III
RIN+
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
PCLK
Camera Data
10 or 12
DATA
HSYNC
VSYNC
Pixel Clock
Image
Sensor
DATA
HSYNC
VSYNC
Pixel Clock
DOUT-
RIN-
Bi-Directional
Control Channel
Encoder
FIFO
SDA
ECU Module
4
GPO[3:0]
SDA
GPO[3:0]
SDA
SCL
GPIO[3:0]
SDA
SCL
4
GPIO[3:0]
SDA
SCL
Microcontroller
Camera Unit
SCL
Figure 3. Application Block Diagram
2
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