DS90UB913Q, DS90UB914Q
SNLS420B –JULY 2012–REVISED APRIL 2013
www.ti.com
Typical Application Diagram
Parallel
Data In
Parallel
Data Out
FPD-Link III
10 or 12
10 or 12
2
2
DSP, FPGA/
µ-Processor/
ECU
HSYNC,
VSYNC
4
Megapixel
Imager/Sensor
HSYNC,
VSYNC
4
DS90UB913Q
DS90UB914Q
Bidirectional
Control Channel
GPO
2
GPIO
2
Bidirectional
Control Bus
Bidirectional
Control Bus
Serializer
Deserializer
Figure 1. Typical Application Circuit
Block Diagrams
10
or
12
10 or
12
DIN
ROUT
HSYNC
VSYNC
R
T
R
T
DOUT+
DOUT-
R
T
R
T
RIN0+
HSYNC
VSYNC
4
GPO[3:0]
4
RIN0-
RIN1+
GPIO[3:0]
Clock
Gen
PCLK
LOCK
Clock
Gen
PCLK
PLL
CDR
PASS
RIN1-
PDB
Timing and
Control
Timing and
Control
PDB
BISTEN
OEN
SDA
SCL
SEL
SDA
SCL
IDx[0]
IDx[1]
MODE
ID[x]
MODE
DS90UB914Q - DESERIALIZER
DS90UB913Q - SERIALIZER
Figure 2. Block Diagram
DS90UB913Q
Serializer
DS90UB914Q
Deserializer
FPD-Link III
Camera Data
Camera Data
DOUT+
DOUT-
10 or 12
RIN+
RIN-
10 or 12
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
Image
Sensor
DATA
DATA
HSYNC
VSYNC
HSYNC
VSYNC
Bi-Directional
PCLK
PCLK
ECU Module
Pixel Clock
Control Channel
Pixel Clock
4
4
GPO[3:0]
GPIO[3:0]
GPO[3:0]
GPIO[3:0]
Microcontroller
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
Camera Unit
Figure 3. Application Block Diagram
2
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