SNLS420B – JULY 2012 – REVISED APRIL 2013
DS90UB913Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
GPO[3]/CLKIN
Pin No.
18
I/O, Type
Input/Output,
LVCMOS
Description
GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
on the Deserializer or can be configured to be the output of the local register setting
on the Serializer. It can also be configured to be the input clock pin when the
DS90UB913Q Serializer is working with an external oscillator. See
section for a detailed description of the DS90UB913/914Q chipsets
working with an external oscillator.
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to V
DDIO
.
Data line for the bidirectional control bus communication
SDA requires an external pull-up resistor to V
DDIO
.
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
SCL
SDA
4
5
Input/Output,
Open Drain
Input/Output,
Open Drain
MODE
8
Device mode select
Input, LVCMOS Resistor to Ground and 10 kΩ pull-up to 1.8V rail. MODE pin on the Serializer can be
w/ pull down
used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in
Input, analog
Device ID Address Select
The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor to
Ground and 10 kΩ pull-up to 1.8V rail. See
ID[x]
6
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
w/ pull down
This pin MUST be tied LOW.
Input/Output,
CML
Input/Output,
CML
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
VSS
DAP
Non-inverting differential output, bidirectional control channel input. The interconnect
must be AC Coupled with a 100 nF capacitor.
Inverting differential output, bidirectional control channel input. The interconnect must
be AC Coupled with a 100 nF capacitor.
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
CML & Bidirectional Channel Driver Power, 1.8V ±5%
Digital Power, 1.8V ±5%
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V
DDIO
.
V
DDIO
can be connected to a 1.8V ±5% or 2.8±10% or 3.3V ±10%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
9 vias.
PDB
9
RES
7
FPD–Link III INTERFACE
DOUT+
DOUT-
POWER AND GROUND
VDDPLL
VDDT
VDDCML
VDDD
VDDIO
10
11
14
28
25
13
12
4
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