DS90UB913Q, DS90UB914Q
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SNLS420B –JULY 2012–REVISED APRIL 2013
MODE
CMLOUTP
CMLOUTN
ROUT[0]
ROUT[1]
ROUT[2]
ROUT[3]
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DAP = GND
VDDCML0
RIN0+
RIN0-
VDDIO2
ROUT[4]
DS90UB914Q
48-Pin WQFN
(Top View)
RES
ROUT[5]
VDDD
RES
ROUT[6]
ROUT[7]
ROUT[8]
ROUT[9]
VDDPLL
SEL
PASS
LOCK
Deserializer - DS90UB914Q — Top View
DS90UB914Q Deserializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[11:0]
11,12,13,14,
15,16,18,19,
21,22,23,24
Outputs,
LVCMOS
Parallel Data Outputs.
Output,
LVCMOS
Horizontal SYNC Output.
Vertical SYNC Output.
Pixel Clock Output Pin.
HSYNC
VSYNC
PCLK
10
9
Output,
LVCMOS
Output,
LVCMOS
8
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
General-purpose input/output pins can be used to control and respond to various
commands. They may be configured to be the input signals for the corresponding
GPOs on the serializer or they may be configured to be outputs to follow local register
settings.
Digital
Input/Output,
LVCMOS
GPI0[1:0]
GPIO[3:2]
27,28
25,26
General purpose input/output pins GPO[2:3] can be configured to be input signals for
GPOs on the Serializer. In addition they can also be configured to be outputs to follow
the local register settings. When the SerDes chipsets are working with an external
oscillator, these pins can be configured only to be outputs to follow the local register
settings.
Digital
Input/Output
LVCMOS
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
Input/Output,
Open Drain
Clock line for the bidirectional control bus communication
SCL
SDA
2
1
SCL requires an external pull-up resistor to VDDIO
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to VDDIO
.
Input/Output,
Open Drain
.
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