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DS90UB913QSQ/NOPB 参数 Datasheet PDF下载

DS90UB913QSQ/NOPB图片预览
型号: DS90UB913QSQ/NOPB
PDF下载: 下载PDF文件 查看货源
内容描述: DS90UB913Q / DS90UB914Q 10-100MHz 10 / 12位DC平衡的FPD -Link的III串行器和解串与双向控制通道 [DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel]
分类和应用: 光电二极管
文件页数/大小: 63 页 / 1331 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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SNLS420B – JULY 2012 – REVISED APRIL 2013
VDDCML1
VDDIO1
GPIO[0]
VDDR
RIN1+
IDx[0]
36
35
34
33
32
31
30
PDB
29
28
27
GPIO[1]
IDx[1]
26
GPIO[2]
RIN1-
25
GPIO[3]
MODE
CMLOUTP
CMLOUTN
VDDCML0
RIN0+
RIN0-
RES
RES
VDDPLL
SEL
PASS
LOCK
37
38
39
40
41
42
43
44
45
46
47
48
10
11
12
1
2
3
4
5
6
7
8
9
24
ROUT[0]
ROUT[1]
ROUT[2]
ROUT[3]
VDDIO2
ROUT[4]
ROUT[5]
VDDD
ROUT[6]
ROUT[7]
ROUT[8]
ROUT[9]
DAP = GND
23
22
21
20
DS90UB914Q
48-Pin WQFN
(Top View)
19
18
17
16
15
14
13
ROUT[11]
VDDSSCG
OSS_SEL
Deserializer - DS90UB914Q — Top View
DS90UB914Q Deserializer Pin Descriptions
Pin Name
ROUT[11:0]
Pin No.
11,12,13,14,
15,16,18,19,
21,22,23,24
10
9
8
I/O, Type
Outputs,
LVCMOS
Output,
LVCMOS
Output,
LVCMOS
Output,
LVCMOS
Parallel Data Outputs.
Description
LVCMOS PARALLEL INTERFACE
HSYNC
VSYNC
PCLK
Horizontal SYNC Output.
Vertical SYNC Output.
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
General-purpose input/output pins can be used to control and respond to various
commands. They may be configured to be the input signals for the corresponding
GPOs on the serializer or they may be configured to be outputs to follow local register
settings.
General purpose input/output pins GPO[2:3] can be configured to be input signals for
GPOs on the Serializer. In addition they can also be configured to be outputs to follow
the local register settings. When the SerDes chipsets are working with an external
oscillator, these pins can be configured only to be outputs to follow the local register
settings.
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to V
DDIO
.
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to V
DDIO
.
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
GPI0[1:0]
27,28
Digital
Input/Output,
LVCMOS
Digital
Input/Output
LVCMOS
GPIO[3:2]
25,26
BIDIRECTIONAL CONTROL BUS - I
2
C COMPATIBLE
SCL
SDA
2
1
Input/Output,
Open Drain
Input/Output,
Open Drain
ROUT[10]
PCLK
SDA
SCL
VSYNC
BISTEN
VDDIO3
HSYNC
OEN
Copyright © 2012–2013, Texas Instruments Incorporated
5
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