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CC2510F8RSP 参数 Datasheet PDF下载

CC2510F8RSP图片预览
型号: CC2510F8RSP
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器, 2.4 GHz射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 244 页 / 2899 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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C2510Fx / CC2511Fx  
second register bank. Thus, in order to use  
more than one register bank, the SPshould be  
initialized to a different location not used for  
data storage.  
SP (0x81) – Stack Pointer  
Bit  
Name  
Reset  
R/W  
Description  
Stack Pointer  
7:0  
SP[7:0]  
0x07  
R/W  
11.4 Instruction Set Summary  
The 8051 instruction set is summarized in  
Table 37. All mnemonics copyrighted © Intel  
Corporation 1980.  
can be anywhere within the 8/16/32 KB  
CODE memory space.  
addr11 – 11-bit destination address.  
Used by ACALL and AJMP. The branch  
will be within the same 2 KB page of  
program memory as the first byte of the  
following instruction.  
rel – Signed (two’s complement) 8-bit  
offset byte. Used by SJMP and all  
conditional jumps. Range is –128 to  
+127 bytes relative to first byte of the  
following instruction.  
The following conventions are used in the  
instruction set summary:  
Rn – Register R7-R0 of the currently  
selected register bank.  
direct – 8-bit internal data location’s  
address. This can be DATA area (0x00  
– 0x7F) or SFR area (0x80 – 0xFF).  
@Ri – 8-bit internal data location, DATA  
area (0x00 – 0xFF) addressed indirectly  
through register R1or R0.  
bit – direct addressed bit in DATA area  
or SFR.  
#data – 8-bit constant included in  
instruction.  
#data16 – 16-bit constant included in  
instruction.  
addr16 – 16-bit destination address.  
Used by LCALL and LJMP. A branch  
The instructions that affect CPU flag settings  
located in PSW are listed in Table 38 on Page  
58. Note that operations on the PSWregister or  
bits in PSWwill also affect the flag settings.  
Mnemonic  
Description  
Hex  
Bytes  
Cycles  
Opcode  
Arithmetic Operations  
ADD A,Rn  
Add register to accumulator  
28-2F  
25  
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
3
ADD A,direct  
ADD A,@Ri  
ADD A,#data  
ADDC A,Rn  
ADDC A,direct  
ADDC A,@Ri  
ADDC A,#data  
SUBB A,Rn  
SUBB A,direct  
SUBB A,@Ri  
SUBB A,#data  
INC A  
Add direct byte to accumulator  
Add indirect RAM to accumulator  
Add immediate data to accumulator  
Add register to accumulator with carry flag  
Add direct byte to A with carry flag  
Add indirect RAM to A with carry flag  
Add immediate data to A with carry flag  
Subtract register from A with borrow  
Subtract direct byte from A with borrow  
Subtract indirect RAM from A with borrow  
Subtract immediate data from A with borrow  
Increment accumulator  
26-27  
24  
38-3F  
35  
36-37  
34  
98-9F  
95  
96-97  
94  
04  
INC Rn  
Increment register  
08-0F  
05  
INC direct  
Increment direct byte  
SWRS055D  
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