C2510Fx / CC2511Fx
XDATA
Register
Description
Address
0xDE20
0xDE22
0xDE24
0xDE26
0xDE28
0xDE2A
USBF0
USBF1
USBF2
USBF3
USBF4
USBF5
Endpoint 0 FIFO
Endpoint 1 FIFO
Endpoint 2 FIFO
Endpoint 3 FIFO
Endpoint 4 FIFO
Endpoint 5 FIFO
Table 36: Overview of Endpoint FIFO Registers
11.2.4 XDATA Memory Access
In some 8051 implementations, this type of
XDATA access is performed using P2 to give
the most significant address bits. Existing
software may therefore have to be adapted to
make use of MPAGE instead of P2.
The CC2510Fx/CC2511Fx provides an additional
SFR named MPAGE. This register is used
during instructions MOVX A,@Ri and MOVX
@Ri,A. MPAGE gives the 8 most significant
address bits, while the register Ri gives the 8
least significant bits.
MPAGE (0x93) – Memory Page Select
Bit
Name
Reset
R/W
Description
7:0
MPAGE[7:0]
0x00
R/W
Memory page, high-order bits of address in MOVX instruction
11.2.5 Memory Arbiter
A control register MEMCTR is used to control
the flash cache. The MEMCTR register is
described below.
The CC2510Fx/CC2511Fx includes a memory
arbiter which handles CPU and DMA access to
all memory space.
MEMCTR (0xC7) – Memory Arbiter Control
Bit
Name
Reset
R/W
Description
7:2
0
R/W
Not used
1
0
R/W
Flash cache disable. Invalidates contents of instruction cache and forces all
instruction read accesses to read straight from flash memory. Disabling will
increase power consumption and is provided for debug purposes.
CACHDIS
0
1
Cache enabled
Cache disabled
0
1
R/W
Flash prefetch disable. When set prefetch of flash data is disabled, when
cleared the next two bytes in flash are fetched when last byte in cache is
read.
PREFDIS
0
1
Prefetch enabled
Prefetch disabled
SWRS055D
Page 51 of 243
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