C2510Fx / CC2511Fx
Instruction
ADD
CY
x
OV
x
x
x
x
x
-
AC
x
x
x
-
ADDC
x
SUBB
x
MUL
0
0
x
DIV
-
DA
-
RRC
x
-
-
RLC
x
-
-
SETB C
CLR C
CPL C
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
CJNE
1
x
-
-
-
-
x
-
-
x
-
-
x
-
-
x
-
-
x
-
-
x
-
-
x
-
-
“0” = Clear to 0, “1” = Set to 1, “x” = Set to 1/Clear to 0, “-“ = Not affected
Table 38: Instructions that Affect Flag Settings
11.5 Interrupts
The CPU has 18 interrupt sources. Each
source has its own request flag located in a
set of Interrupt Flag SFRs. Each interrupt can
be individually enabled or disabled. The
definitions of the interrupt sources and the
Note that some peripherals have several
events that can generate the interrupt request
associated with that peripheral. This applies to
P0, P1, P2, DMA, Timer 1, Timer 2, Timer 3,
Timer 4, and Radio. These peripherals have
interrupt mask bits for each internal interrupt
source in the corresponding SFRs. Note that
I2S has its own interrupt enable bits even if it
has only one event per interrupt. For the
peripherals that have their own mask bits, one
or more of these bits must be set for the
associated CPU interrupt flag to be asserted.
interrupt vectors are given in
Table 39.
I2S and USART1 share interrupts. On the
CC2511Fx USB shares interrupt with Port 2
inputs. The interrupt aliases for I2S and USB
are listed in Table 40. However, in the
following sections the original interrupt names,
masks, and flags listed in
the ones used.
Table 39 are
In order to use any of the interrupts in the
CC2510Fx/CC2511Fx the following steps must be
taken:
The interrupts are grouped into a set of priority
level groups with selectable priority levels.
The interrupt enable registers are described in
Section 11.5.1 and the interrupt priority
settings are described in Section 11.5.2 on
Page 66.
11.5.1 Interrupt Masking
Each interrupt can be individually enabled or
disabled by the interrupt enable bits in the
Interrupt Enable SFRs IEN0, IEN1, and IEN2.
The Interrupt Enable SFRs are described
below and summarized in
Table 39.
SWRS055D
Page 58 of 243
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