CC2430
Peripherals : DMA Controller
13.5 DMA Controller
periodically transfer samples between ADC
and memory, etc. Use of the DMA can also
reduce system power consumption by keeping
the CPU in a low-power mode without having
to wake up to move data to or from a
peripheral unit (see section 13.1.1.1 for CPU
low power mode). Note that section 11.2.3
describes which SFR registers that are not
mapped into XDATA memory space.
The CC2430 includes a direct memory access
(DMA) controller, which can be used to relieve
the 8051 CPU core of handling data
movement operations thus achieving high
overall performance with good power
efficiency. The DMA controller can move data
from a peripheral unit such as ADC or RF
transceiver to memory with minimum CPU
intervention.
The main features of the DMA controller are as
follows:
The DMA controller coordinates all DMA
transfers, ensuring that DMA requests are
prioritized appropriately relative to each other
and CPU memory access. The DMA controller
contains a number of programmable DMA
channels for memory-memory data movement.
•
•
Five independent DMA channels
Three configurable levels of DMA channel
priority
•
•
31 configurable transfer trigger events
Independent control of source and
destination address
The DMA controller controls data transfers
over the entire address range in XDATA
memory space. Since most of the SFR
registers are mapped into the DMA memory
space, these flexible DMA channels can be
used to unburden the CPU in innovative ways,
e.g. feed a USART with data from memory or
•
•
Single, block and repeated transfer modes
Supports length field in transfer data
setting variable transfer length
Can operate in either word-size or byte-
size mode
•
13.5.1
DMA Operation
There are five DMA channels available in the
the channel the trigger will be lost. If more than
one DMA channels are armed simultaneously,
the time for all channels to be configured will
be longer (sequential read from memory). If all
5 are armed it will take 45 system clocks and
channel 1 will first be ready, then channel 2
and lastly channel 0 (all within the last 8
system clocks). There are 31 possible DMA
trigger events, e.g. UART transfer, Timer
overflow etc. The trigger event to be used by a
DMA channel is set by the DMA channel
configuration thus no knowledge of this is
available until after configuration has been
read. The DMA trigger events are listed in
Table 41.
DMA controller numbered channel to
0
channel 4. Each DMA channel can move data
from one place within the DMA memory space
to another i.e. between XDATA locations.
In order to use a DMA channel it must first be
configured as described in sections 13.5.2 and
13.5.3. Figure 18 shows the DMA state
diagram.
Once a DMA channel has been configured it
must be armed before any transfers are
allowed to be initiated. A DMA channel is
armed by setting the appropriate bit in the
DMA Channel Arm register DMAARM.
In addition to starting a DMA transfer through
the DMA trigger events, the user software may
force a DMA transfer to begin by setting the
corresponding DMAREQbit.
When a DMA channel is armed a transfer will
begin when the configured DMA trigger event
occurs. Note that the time to arm one channel
(i.e. get configuration data) takes 9 system
clocks, thus if DMAARM bit set and a trigger
appears within the time it takes to configure
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 88 of 211
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