CC2430
Peripherals : I/O ports
Table 40: Peripheral I/O Pin Mapping
P0
7
P1
P2
Periphery /
Function
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
T
ADC
C
SS
CT
M0
TX
2
M0
TX
C
MI
RX
SS
CT
0
USART0 SPI
Alt. 2
M0
TX
C
MI
C
SS
CT
RT
MI
RX
USART0 UART
Alt. 2
RX
SS
CT
RT
USART1 SPI
Alt. 2
MI
M0
TX
RT
1
USART1 UART
Alt. 2
RX
RT
TIMER1
Alt. 2
0
1
2
1
0
TIMER3
Alt. 2
1
0
1
0
TIMER4
Alt. 2
1
0
32.768 kHz
XOSC
Q2
Q1
D
C
D
D
DEBUG
13.4.6.1
Timer 1
peripherals to port 0. When set to 10 or 11 the
timer 1 channels have precedence.
PERCFG.T1CFG selects whether to use
alternative 1 or alternative 2 locations.
P2SEL.PRI1P1 and P2SEL.PRI0P1 select
the order of precedence when assigning
several peripherals to port 1. The timer 1
channels have precedence when the former is
set low and the latter is set high.
In Table 40, the Timer 1 signals are shown as
the following:
•
•
•
0 : Channel 0 capture/compare pin
1 : Channel 1 capture/compare pin
2 : Channel 2 capture/compare pin
P2DIR.PRIP0
precedence
selects
when
the
assigning
order
of
several
13.4.6.2
Timer 3
PERCFG.T3CFG selects whether to use
alternative 1 or alternative 2 locations.
•
•
0 : Channel 0 compare pin
1 : Channel 1 compare pin
In Table 40, the Timer 3 signals are shown as
the following:
P2SEL.PRI2P1 selects the order of
precedence when assigning several
peripherals to port 1. The timer 3 channels
have precedence when the bit is set.
13.4.6.3
Timer 4
PERCFG.T4CFG selects whether to use
alternative 1 or alternative 2 locations.
•
•
0 : Channel 0 compare pin
1 : Channel 1 compare pin
In Table 40, the Timer 4 signals are shown as
the following:
P2SEL.PRI1P1 selects the order of
precedence when assigning several
peripherals to port 1. The timer 4 channels
have precedence when the bit is set.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 80 of 211
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