CC2430
Peripherals : Flash Controller
13.3.4
Flash Write Timing
The Flash Controller contains
a
timing
The value set in the FWT.FWT[5:0] shall be
set according to the CPU clock frequency. The
initial value held in FWT.FWT[5:0] after a
reset is 0x2A which corresponds to 32 MHz
CPU clock frequency.
generator, which controls the timing sequence
of flash write and erase operations. The timing
generator uses the information set in the Flash
Write Timing register, FWT.FWT[5:0], to set
the internal timing. FWT.FWT[5:0] must be
set to a value according to the currently
selected CPU clock frequency.
The FWT values for the 16 MHz and 32 MHz
CPU clock frequencies are given in Table 39.
Table 39: Flash timing (FWT) values
CPU clock
FWT
frequency (MHz)
16
32
0x15
0x2A
13.3.5
Flash DMA trigger
The Flash DMA trigger is activated when flash
data written to the FWDATA register has been
written to the specified location in the flash
memory, thus indicating that the flash
controller is ready to accept new data to be
written to FWDATA. In order to start first
transfer one has to set the FCTL.WRITEbit to
1. The DMA and the flash controller will then
handle all transfer automatically for the defined
block of data (LEN in DMA configuration). It is
further important that the DMA is armed prior
to setting the FCTL.WRITE bit and that the
trigger
source
set
to
FLASH
(TRIG[4:0]=10010) and that the DMA has
high priority so the transfer in not interrupted. If
interrupted for more than 40 µs the write will
not complete as write flag is reset (not allowed
to access one word for write for more than 40
µs thus protection to turn the write off).
13.3.6
Flash Controller Registers
The Flash Controller registers are described in
this section.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 76 of 211
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