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CC2430F32RTC 参数 Datasheet PDF下载

CC2430F32RTC图片预览
型号: CC2430F32RTC
PDF下载: 下载PDF文件 查看货源
内容描述: 真正的系统级芯片解决方案的2.4 GHz IEEE 802.15.4 / ZigBee的 [A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee]
分类和应用: 电信集成电路
文件页数/大小: 212 页 / 1862 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC2430  
Peripherals : Power Management and clocks  
PCON (0x87) – Power Mode Control  
Bit  
Name  
-
Reset  
R/W  
Description  
7:2  
0x00  
R/W  
Not used.  
1
0
0
0
R0  
Not used, always read as 0.  
-
R0/W  
H0  
Power mode control. Writing a 1 to this bit forces CC2430 to enter  
IDLE  
the power mode set by SLEEP.MODE(note that MODE= 0x00  
will stop CPU core, no peripherals, activity when this bit is  
enabled). This bit is always read as 0  
All enabled interrupts will clear this bit when active and CC2430  
will reenter PM0.  
SLEEP (0xBE) – Sleep Mode Control  
Bit  
Name  
Reset  
R/W  
Description  
7
OSC32K_CALDIS  
0
R/W  
Disable 32 kHz RC oscillator calibration  
0 – 32 kHz RC oscillator calibration is enabled  
1 – 32 kHz RC oscillator calibration is disabled.  
The setting of this bit to 1 does not take effect until high-frequency  
RC oscillator is chosen as source for system clock, i.e.  
CLKCON.OSC set to 1.  
Note: this bit is not retained in PM2 and PM3. After re-entry to PM0  
from PM2 or PM3 this bit will be at the reset value 0  
6
0
R
XOSC stable status:  
XOSC_STB  
0 – XOSC is not powered up or not yet stable  
1 – XOSC is powered up and stable.  
Note that an additionl wait time of 64 µs is needed after this bit has  
been set until true stable state is reached.  
5
0
R
R
High-frequency RC oscillator (HF RCOSC) stable status:  
HFRC_STB  
RST[1:0]  
0 – HF RCOSC is not powered up or not yet stable  
1 – HF RCOSC is powered up and stable  
4:3  
XX  
Status bit indicating the cause of the last reset. If there are multiple  
resets, the register will only contain the last event.  
00 – Power-on reset  
01 – External reset  
10 – Watchdog timer reset  
2
1
R/W  
H0  
High-frequency (32 MHz) crystal oscillator and High-frequency (16  
MHz) RC oscillator power down setting. If there is a calibration in  
progress and the CPU attempts to set this bit, the bit will be  
updated at the end of calibration:  
OSC_PD  
0 – Both oscillators powered up  
1 – Oscillator not selected by CLKCON.OSC bit powered down  
1:0  
00  
R/W  
Power mode setting:  
MODE[1:0]  
00 – Power mode 0  
01 – Power mode 1  
10 – Power mode 2  
11 – Power mode 3  
CC2430 Data Sheet (rev. 2.1) SWRS036F  
Page 67 of 211  
 
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