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CC2430F32RTC 参数 Datasheet PDF下载

CC2430F32RTC图片预览
型号: CC2430F32RTC
PDF下载: 下载PDF文件 查看货源
内容描述: 真正的系统级芯片解决方案的2.4 GHz IEEE 802.15.4 / ZigBee的 [A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee]
分类和应用: 电信集成电路
文件页数/大小: 212 页 / 1862 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
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CC2430  
Debug Interface : Debug Lock Bit  
Table 36: Debug Configuration  
Bit  
7-4  
3
Name  
Description  
-
Not used, must be set to zero.  
TIMERS_OFF  
Disable timers. Disable timer operation. This overrides the  
TIMER_SUSPENDbit and its function.  
0
1
Do not disable timers  
Disable timers  
DMA_PAUSE  
2
1
DMA pause  
0
1
Enable DMA transfers  
Pause all DMA transfers  
TIMER_SUSPEND  
Suspend timers. Timer operation is suspended for debug  
instructions and if a step instruction is a branch. If not  
suspended these instructions would result an extra timer  
count during the clock cycle in which the branch is executed  
0
1
Do not suspend timers  
Suspend timers  
SEL_FLASH_INFO_PAGE  
0
Select flash information page (2KB lowest part of flash)  
0
1
Select flash main page (32, 64, or 128 KB)  
Select flash information page (2KB)  
Table 37: Debug Status  
Bit  
Name  
Description  
CHIP_ERASE_DONE  
7
Flash chip erase done  
0
1
Chip erase in progress  
Chip erase done  
PCON_IDLE  
6
5
4
3
2
1
PCON idle  
0
1
CPU is running  
CPU is idle (clock gated)  
CPU_HALTED  
CPU halted  
0
1
CPU running  
CPU halted  
POWER_MODE_0  
HALT_STATUS  
DEBUG_LOCKED  
OSCILLATOR_STABLE  
Power Mode 0  
0
1
Power Mode 1-3 selected  
Power Mode 0 selected  
Halt status. Returns cause of last CPU halt  
0
1
CPU was halted by HALT debug command  
CPU was halted by hardware breakpoint  
Debug locked. Returns value of DBGLOCK bit  
0
1
Debug interface is not locked  
Debug interface is locked  
Oscillators stable. This bit represents the status of the  
SLEEP.XSOC_STBand SLEEP.HFRC_STBregister bits.  
0
1
Oscillators not stable  
Oscillators stable  
STACK_OVERFLOW  
0
Stack overflow. This bit indicates when the CPU writes to  
DATA memory space at address 0xFF which is possibly a  
stack overflow  
0
1
No stack overflow  
Stack overflow  
12.4.3  
Hardware Breakpoints  
The debug command SET_HW_BRKPNT is  
used to set a hardware breakpoint. The  
CC2430 supports up to four hardware  
breakpoints. When a hardware breakpoint is  
enabled it will compare the CPU address bus  
with the breakpoint. When a match occurs, the  
CPU is halted.  
When issuing the SET_HW_BRKPNT, the  
external host must supply three data bytes that  
define the hardware breakpoint. The hardware  
breakpoint itself consists of 18 bits while three  
bits are used for control purposes. The format  
of  
the  
three  
data  
bytes  
for  
the  
SET_HW_BRKPNT command is as follows.  
CC2430 Data Sheet (rev. 2.1) SWRS036F  
Page 63 of 211  
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