CC2430
Debug Interface
: Debug interface and Power Modes
The first data byte consists of the following:
The second data byte consists of bits 15-8 of
the hardware breakpoint.
•
•
•
•
bits 7-5
bits 4-3
bit 2
: unused
The third data byte consists of bits 7-0 of the
hardware breakpoint. Thus the second and
third data byte sets the CPU CODE address to
stop execution at.
: breakpoint number; 0-3
: 1=enable, 0=disable
: Memory bank bits. Bits 17-16
of hardware breakpoint.
bits 1-0
12.4.4
Flash Programming
Programming of the on-chip flash is performed
via the debug interface. The external host
must initially send instructions using the
DEBUG_INSTR debug command to perform
the flash programming with the Flash
Controller as described in section 13.3 on
page 71.
12.5 Debug interface and Power Modes
The debug interface can be used in all power
modes, but with limitations. When enabling a
power mode the system will act as normally
with the exeption that the digital voltage
regulator is not turned off, thus power
consumption when debugging power modes is
higher than expected. The limitation when
debugging power modes 2 and 3 is that the
chip will stop operating when woke up, thus a
HALT and a RESUME command is needed to
continue the SW execution. Pleas note that
PM1 works as expected, also after chip is
woke up.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 64 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
