W681308
XXXX PRODUCT DESCRIPTION
Activation of reset
The Idle mode can also be exited by activating the reset. The device can be put into reset either by applying a high on the
external RST pin, a Power on reset condition or a Watchdog timer reset. The external reset pin has to be held high for at
least two machine cycles i.e. 8 clock periods to be recognized as a valid reset. In the reset condition the program counter is
reset to 0000h and all the SFRs are set to the reset condition. Since the clock is already running there is no delay and
execution starts immediately. In Idle mode, the Watchdog timer continues to run, and if enabled, a time-out will cause a
watchdog timer interrupt which will wake up the device. The software must reset the Watchdog timer in order to preempt the
reset which will occur after 512 clock periods of the time-out. When the W681308 is exiting from an idle mode with a reset,
the instruction following the one which put the device into idle mode is not executed. So there is no danger of unexpected
writes.
8.4
There are two ways to put device into reset state: external reset and watchdog reset.
8.4.1 External Reset
Reset Conditions
The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST pin must be held for at
least 2 machine cycles to ensure detection of a valid RST high. The reset circuitry then synchronously applies the internal
reset signal. Thus the reset is synchronous operation and requires the clock to be running to cause an external reset. Once
the device is in reset condition, it will remain so long as RST is 1. Even after RST is deactivated, the device will continue to
be in reset state for up to two machine cycles, and then begin program execution from 0000h.
8.4.2
Watchdog Reset
The Watchdog timer is a free-running timer with programmable time-out intervals. The user can clear the watchdog timer at
any time, causing it to restart the count. When the time-out interval is reached an interrupt flag is set. If the Watchdog reset is
enabled and the watchdog timer is not cleared, then 512 clocks from the flag being set, the watchdog timer will generate a
reset. This places the device into the reset condition. The reset condition is maintained by hardware for two machine cycles.
Once the reset is removed the device will begin execution from 0000h.
8.5
Interrupts
The W681308 MCU has three priority levels interrupt structure with 7 interrupt sources. Each of the interrupt sources has an
individual priority bit, flag, interrupt vector and enable bit. Additionally, all the interrupts can be globally enabled or disabled.
Source
Flag
IE0
Priority
Vector address
0003h
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
1 (highest)
TF0
2
000Bh
IE1
3
0013h
TF1
4
001Bh
RI + TI
TF2 + EXF2
WDIF
5
6
0023h
Timer 2 Overflow
Watchdog Timer
002Bh
7 (lowest)
0063h
Table 3 Interrupt Priority Structure
23
Rev1.2
NUVOTEM TALEMA [ NUVOTEM TALEMA ]
