SyncMOS Technologies International. Inc.
SM79108
The clock frequency of LCD driver is obtained using the following formula:
Fclk_lcd = { [Fosc / 2 ] / 32 x PRESCALER }
The frame of LCD driver is determined as follows:
Frame = Fclk_lcd / 256
The typical range of Fframe is:
1026HZ ~ 8HZ at 16MHz (Fosc = 8MHz)
7.2 LCD Buffer Registers (LCDB0 ~ LCDB6, 0E1H ~ 0E7H)
Addressing Map of the LCD buffer registers is shown as following:
com3
Bit7
com2
Bit6
com1
Bit5
com0
Bit4
com3
Bit3
com2
Bit2
com1
Bit1
com0
Bit0
Mnemonic address
LCDB0
LCDB1
LCDB2
LCDB3
LCDB4
LCDB5
LCDB6
E1H
E2H
E3H
E4H
E5H
E6H
E7H
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
7.3 Timing chart of LCD driver output
The 14 segment drivers and the 4 common drivers are 4-level outputs that switch between Vcc and the V1, V2
and Vss LCD driver voltages levels.
The output states are determined by the display data values which stored in the LCD buffer registers (0E1H
~0E7H).
The LCD driver's outputs are used to drive a 1/3-bias, 1/4-duty LCD panel.
7.4 The Output Control of Segments and Commons
Port 2 Configuration Register (P2CON) control COM0 ~ COM3 and SEG0 ~ SEG3 output; Port 0 Configuration
Register (P0CON) controls SEG6 ~ SEG13 outputs.
The bit 5 of LCD Control Register control the SEG4 and SEG5 outputs.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/26
Ver 2.1 SM79108 08/2006
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
