SyncMOS Technologies International. Inc.
SM79108
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
0.45V
70%Vdd
20%Vdd-0.1V
TCLCX
TCHCX
TCHCL
TCLCH
Tm.I External Program Memory Read Cycle
TPLPH
#PSEN
TLHLL
TAVLL
TLLPL
TPXIZ
TPXIX
ALE
TPLAZ
TLLAX
TPLIV
Instruction. IN
A0 - A7
A0 - A7
PORT 0
TAVIV
A8 - A15
A8 - A15
PORT 2
Tm.II External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
PORT 0
PORT 2
TAVLL
TRHDZ
TRHDX
DATA IN
TLLAX
TRLDV
TRLAZ
A0 - A7
from Ri or DPL
A0 - A7
from PCL
INSTRL
IN
TAVYL
TAVDV
A8 - A15 from PCH
P2.0 - P2.7 or A8 - A15 from DPH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
20/26
Ver 2.1 SM79108 08/2006
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
