SyncMOS Technologies International. Inc.
SM79108
ADCSS[1:0]: ADCSS channel select bit.
ADCSS1
ADCSS0
ADC_CLK
Fosc / 8 (below 20MHz)
Fosc / 16
0
0
1
1
0
1
0
1
Fosc / 32
Fosc / 64
CH[1:0] : ADC channel select bit. These bits are used to select one of the ADC channels.
CH1
CH0
Input select
CH0
0
0
1
1
0
1
0
1
CH1
CH2
CH3
Note: ADC_CLK frequency range 500KHz ~ 2.5MHz
ADC registers - ADC Data Register (ADCD, 8FH)
bit-7
AD7
R
bit-0
AD0
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
AD1
R
Read /Write:
Reset value:
0
0
0
0
0
0
0
0
ADC puts the result in the ADC Data Register (ADCD, 8FH) after each conversion. The ADCD register is read only regis-
ter. The content of the ADCD will be 00H after reset.
Ex : Osc = 20MHz ADCSS[1:0] = 00
ADC input clock = 20/8 = 2.5MHz (Max)
One conversion time = 20 / 2.5MHz = 8us
ADC Max sample reta = 2.5MHz / 20 = 125KHz
Port 3 Configuration Register (P3CON, 9DH)
bit-7
ADCE3
R/W
0
bit-0
ADCE2
R/W
0
ADCE1
R/W
0
ADCE0
R/W
0
Unused Unused
Unused
Unused
Read /Write:
Reset value:
-
-
-
-
*
*
*
*
Set ADCE3
ADCE3
= 1 enables the ADC function on pin P3.7/A15/ADC3,
= 0 disables the ADC function on pin P3.7/A15/ADC3,
= 1 enables the ADC function on pin P3.6/A14/ADC2,
= 0 disables the ADC function on pin P3.6/A14/ADC2,
Set ADCE2
ADCE2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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Ver 2.1 SM79108 08/2006
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
