SyncMOS Technologies International, Inc.
SM59264
8-Bits Micro-controller
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
MASTER: If set the MASTER bit, the module will generate a start condition to the SDA and SCL lines and send out the
calling address which is stored in the IADR register. But if the TFIF flag is set when transmit fail occurs on the
lines, the module will discard the master mode by clearing the MASTER bit and release both SDA and SCL
lines immediately. This bit can also be cleared by writing zero to it or when the NAKIF is set. When the
MASTER bit is cleared either by set NAKIF or software the module will generate a stop condition to the lines
after the current byte transmission is done, and IGNORE the TWSITDB data when next TWSI transmit cycle if
this data had not been transmit out. Reset clears this bit.
TXAK: The bit (TXAK) control the acknowledge transmit in RECEIVE mode, if it is cleared, a low (Ack) will be
generated at the 9th clock after receiving 8 bits data. When TXAK is set, a high (NoAck) will be generated at the
9th clock after receiving 8 bits data. Reset clears this bit.
TWSI Address Register (TWSIA, $C1)
bit-7
bit-0
Read:
Write:
TWSIA.7 TWSIA.6 TWSIA.5 TWSIA.4 TWSIA.3 TWSIA.2 TWSIA.1 EXTADDR
Reset value:
1
0
1
0
0
0
0
0
TWSIA[7:1] : These 7 bits can be the chip address in slave mode or the calling address when in master mode. This
register is set as $A0 upon reset.
EXTADDR : The EXTAD bit is set to expand the chip address of this module. When it is one, the module will
acknowledge the general call address $00 and the address comparison circuit will only compare the 4
MSB bits in the LADR register. When it is zero, the module will only acknowledge to the specific address
which is stored in the IADR register. It is zero after reset.
TWSI Control Register (TWSIC1, $C2)
bit-7
bit-0
Read:
Write:
Reset value:
TWSIE
0
-
-
-
BB
0
TWSIFS2 TWSIFS1 TWSIFS0
0
0
0
0
0
1
TWSIE: If this TWSI module Enable bit (IE1) is set, the TWSI module is enable. If the IE1 is clear, the interface is
disable and all flags will restore its reset default states. Reset clears this bit.
BB : The Bus Busy Flag is set after a start condition is detected, and is reset when a stop condition is detected. Reset
clears this bit.
TWSIFS[2:0] :The three Baud Rate select bits will select one of the eight clock rates as the master clock when the
module is in master mode. The serial clock frequency is equal to the external clock divided by the
certain divider. These bits are cleared upon reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM59264 08/2006
22
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
