SyncMOS Technologies International, Inc.
SM59264
8-Bits Micro-controller
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
TWSI Transmit Data Buffer (TWSITxD, $C4)
Bit-7
bit-0
Read:
Write:
TWSI
TxD.7
TWSITxD.6 TWSITxD.5 TWSITxD.4 TWSITxD.3 TWSITxD.2 TWSITxD.1 TWSITxD.0
Reset value:
0
0
0
0
0
0
0
0
The data written into this register will be automatically downloaded to the shift register when the module detects a
calling address is matched and the bit 0 of the received data is one (Slave transmit mode) or when the data in the shift
register has been transmitted with received acknowledge bit (RXAK) =0 in transmit mode. So if the program doesn’t
write the data into the TWSITDB register before the matched calling address is detected or the shift register has been
transmitted out, the module will pull down the SCL line (after receive ackowledge bit). If write a data to the TWSITxD
register, then the written data will be downloaded to the shift register immediately and the module will release the SCL
line, and the TXIF flag is set to generate another interrupt request for next data. So the S/W may need to write the next
data to the TWSITxD register and for the auto downloading of data to the shift register after the data in the shift register
is transmitted over again with RXAK=0. If the module receiver non-acknowledge (RXAK=1), the module will release
the SDA line for master to generate Stop or Repeated Start conditions.
TWSI Receive Data Buffer (TWSIRxD, $C5)
Bit-7
bit-0
Read:
Write:
TWSIRD.7 TWSIRD.6 TWSIRD.5 TWSIRD.4 TWSIRD.3 TWSIRD.2 TWSIRD.1 TWSIRD.0
Reset value:
0
0
0
0
0
0
0
0
The TWSI Receive Data Buffer (TWSIRxD) contains the last received data when the MATCH flag is one or the calling
address from master when the MATCH flag is zero. The TWSIRxD register will be updated after a data byte is received
and the previous received data had been read out, otherwise the DDC module will pull down to SCL line to inhabit the
next data transfer. It is a read-only register. The read operation of this register will clear the RXIF flag. After the RXIF
flag is cleared, the register can load the received data again and set the RXIF flag the venerate interrupt request for
reading the newly received data.
7.2 TWSI Interrupt
The TWSI module will generate TWSI interrupt once hardware circuit detects START signal of TWSISDA and
TWSISCL. The TWSI interrupt vector locates at $3B. There are three SFRs for configuring TWSI interrupt: IP1, IE1
and IFR. To use TWSI interrupt is the same as to use other generic 8052 interrupts. That means using ETWSI of IE1
for enable/disable TWSI interrupt, using PTWSI for assign TWSI interrupt priority. Whenever TWSI interrupt occurs,
TWSIIF will be set to 1. After TWSI interrupt subroutine (vector) been executed, TWSIIF will be cleared to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM59264 08/2006
24
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
