SyncMOS Technologies International, Inc.
SM59264
8-Bits Micro-controller
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
TWSIFS[2:0]
0:0:0
Baud Rate
Unused
400K
0:0:1
0:1:0
200K
0:1:1
100K
1:0:0
50K
1:0:1
25K
1:1:0
1:1:1
12.5K
6.25K
Note: clock source is from external (12M Hz).
TWSI Control Register 2 (TWSIC2, $C3)
bit-7
bit-0
MATCH
Note1
SRW
RSTART
Note2
MRW
Note3
-
-
-
-
Note1
Read/Write:
Reset value:
1
0
0
0
0
0
0
0
Note1:Read and Writer’0’ only
Note2:Read only
Note3:Read and Writer
MATCH : The MATCH flag is set when the first received data (following START signal) in the IRDB register which
matches with the address or its extended addresses (EXTAD=1) specified in the IADR.
SRW : The Slave Rw bit will indicate the data direction of TWSI protocol. It is updated after the calling address is
received in the SLAVE mode. When it is one, the master will read the data from TWSI module, so the module
is in transmit mode. When it is zero, the master will send data to the TWSI module, the module, the module is
in receive mode. The reset clear it.
RESTART: If set this RESTART bit in master mode (MASTER=1), the module will generate a start condition to the
SDA and SCL lines (after current ACK bit) and send out the calling address which is stored in the
TWSIADR register. But if the TFIF flag is set when transmit fail occurs on the lines, the module will discard
the master mode by clearing the MASTER bit and release bit SDA and SCL lines immediately. This bit will
clear automatically after generate a start condition to the SDA and SCL lines. Reset clears this bit.
MRW : This MRW bit will be transmitted out as the bit 0 of the calling address when the module sets the MAS TER bit
to enter the master mode. It will also determine the transfer direction of the following data bytes. When it is one,
the module is in master receive mode. When it is zero, the module is in master transmit mode. Reset clears this
bit.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM59264 08/2006
23
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
