SyncMOS Technologies International, Inc.
SM59264
8-Bits Micro-controller
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7
WDR
R/W
0
bit-0
ALEI
R/W
0
Unused
Unused
Unused
DFEN
R/W
0
ISPE
R/W
0
OME
R/W
0
Read / Write:
Reset value:
-
*
-
*
-
*
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened
5. Reduce EMI Function
The SM59264 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function
will inhibit the clock signal in Fosc/6Hz output to the ALE pin.
6. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module contains 1 kind of PWM sub module: SPWM (Specific PWM).
SPWM has five 8-bit channels.
6.1 SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit
binary rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse
length of the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle
frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the
BRM is to generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit
SPWM clock speed. The SPFS[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock,
Fosc/2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is
[Fosc/2^(SPFS[1:0]+1)]/32.
6.2 SPWM Registers - P1CON, SPWMC, SPWMD[3:0]
SPWM Registers - Port1 Configuration Register (P1CON, $9B)
bit-7
bit-0
Unused
TWSIDAE TWSICLE SPWME3 SPWME2 SPWME1 SPWME0
Unused
Read / Write:
Reset value:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
-
*
-
*
TWSIDAE: When the bit set to one ,the corresponding TWSIDA pin is active as TWSIDA function. When the bit reset
to zero, the corresponding TWSIDA pin is active as I/O pin. Four bits are cleared upon reset.
TWSICLE: When the bit set to one ,the corresponding TWSICLE pin is active as TWSICLE function. When the bit reset
to zero, the corresponding TWSICLE pin is active as I/O pin. Four bits are cleared upon reset.
SPWME[3:0]: When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to
zero, the corresponding SPWM pin is active as I/O pin. Four bits are cleared upon reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM59264 08/2006
18
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
