SyncMOS Technologies International, Inc.
SM59264
8-Bits Micro-controller
7. TWSI Interface (Two Wire Serial wInithte1r2f8aKcBef)lash & 1KB RAM & TWSI & SPWM embedded
The TWSI module uses the SCL (clock) and the SDA (data) line to communicate with external TWSI interface. Its
speed can be selected to 6.25K~400Kbps by software setting the BR[2..0] contrtol bit. The TWSI module provided 4
interrupts (Rx, Tx, NonAck, TxFail). It will generate and/or detects START, repeated START and STOP signals
automatically in master mode. The maximum communication length and the number of devices that can be connected
are limited by a maximum bus capacitance of 400pF.
7.1 TWSI Registers
TWSI Status Register (TWSIS, $C0)
bit-7
bit-0
RXIF
Note1
0
TXIF
Note1
0
TFIF
Note1
0
NAKIF
Note1
0
-
RXAK
Note2
1
MASTER
Note3
0
TXAK
Note3
0
Read / Write:
Reset value:
Unused
Note1:Read and Writer’0’ only
Note2:Read only
Note3:Read and Writer
RXIF: The data Receive Interrupt Flag (RXIF) is set after the TWSIRDB (TWSI Receive Data Buffer) is loaded with a
newly receive data. Once the IRDB is loaded with received data, no more received data can be loaded to the
TWSIRDB register again.
TXIF: The data Transmit Interrupt Flag is set when the data of the TWSITDB register is downloaded to the shift register
or Master Transmit mode the IADR is downloaded to the shift register. It is software’s responsibility to fill the
TWSITDB register with new data when this bit is set. This bit is cleared by writing zero to it, write data to
TWSITDB or when reset.
TFIF: The Transmit Fail Interrupt Flag is set when the data transmit is fail, which as set MASTER bit when the BB has
been set by detecting the start condition on the lines or when the module is transmitting a One to SDA line but
detected a Zero from SDA line in master mode, which is also called arbitration loss. This bit is cleared by writing
Zero to it or by reset.
NAKIF: The NonAcknowledge Interrupt Flag is only set in the master transmit mode when there is no acknowledge bi
detected after one byte data or calling address is transferred. This bit is cleared by writing Zero to it or by reset.
RXAK: If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the
completion of 8 data bits transmission on the bus. If RXAK is high, it indicates no acknowledge signal has been
detected at the 9th clock. Then the module will release the SDA line for the master to generate Stop or Repeated
Start condition. It is set upon reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM59264 08/2006
21
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
