SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-
start to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
Clear
WDTF = 0
1. Power on reset
2. External reset
3. Software write “0”
WDTF
Set WDTF = 1
23KHz RC
oscillator
CWDTR = 0
CWDTR = 1
WDTCLK
1
WDT time-out
reset
TAKEY
(55, AA, 5A)
WDT
time-out
select
2WDTM
WDT
Counter
WDT time-out
Interrupt
WDTM[3:0]
Enable/Disable
WDT
Refresh
WDT Counter
WDTC
Enable WDTC
write attribute
WDTK
(0x55)
WDTEN
Fig. 10-1: Watchdog timer block diagram
Mnemonic
Description
Dir.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
Watchdog Timer
Time Access
Key register
Watchdog timer
control register
Watchdog timer
refresh key
TAKEY
WDTC
WDTK
F7h
B6h
B7h
TAKEY [7:0]
-
00H
04H
00H
-
CWDTR
WDTE
WDTM [3:0]
Address: F7h
WDTK[7:0]
Mnemonic: TAKEY
7
6
5
4
3
2
1
0
Reset
00H
TAKEY [7:0]
Watchdog timer control register (WDTC) is read-only by default; software must write three specific values 55h, AAh and
5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A SM59A16U1 04/12/2013
- 72 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
