SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
11. Interrupt
The SM59A16U1 provides 14 interrupt sources with four priority levels. Each source has its own request flag(s) located
in a special function register. Each interrupt requested by the corresponding flag could individually be enabled or
disabled by the enable bits in SFR‟s IEN0, IEN1, and IEN2.
When the interrupt occurs, the engine will vector to the predetermined address as given in Table 11-1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have
been next when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless
of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then
samples are polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then
interrupt request flag is set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an
LCALL to appropriate vector address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an
interrupt is 7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the
LCALL.
Table 11-1: Interrupt vectors
Interrupt Vector
Address
Interrupt Number
*(use Keil C Tool)
Interrupt Request Flags
1
2
IE0 – External interrupt 0
0003h
000Bh
0013h
001Bh
0023h
002Bh
0043h
004Bh
0053h
005Bh
0063h
006Bh
0073h
007Bh
0083h
008Bh
0093h
0
1
TF0 – Timer 0 interrupt
3
IE1 – External interrupt 1
TF1 – Timer 1 interrupt
2
4
3
5
RI0/TI 0– Serial channel 0 interrupt
TF2/EXF2 – Timer 2 interrupt
PWMIF – PWM interrupt
SPIIF – SPI interrupt
4
6
5
7
8
8
9
9
ADCIF – A/D converter interrupt
KBIIF – keyboard Interface interrupt
LVIIF – Low Voltage Interrupt
IICIF – IIC interrupt
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
USB interrupt
USBRSM interrupt
RI1/TI1 – Serial channel 1 interrupt
WDT – Watchdog interrupt
Comparator interrupt
*See Keil C about C51 User‟s Guide about Interrupt Function description
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 75 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
